Transcript Real-Traffic Based Verification for Gigabit

Real-Traffic Based Verification for
Gigabit-Switch Chipset
전정범
1999/9/27
Outline
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Summary of previous presentation
Virtual network environment vs. Real-traffic based environment
Introduction to VCS
Current status
Further works
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Gigabit-Switch Chipset & Configuration
Network
Processor
NI
NI
Rx
Port
M
A Controller
#0
C
Tx
Rx
Tx
NI
Port
M
Controller A
#4
C
NI
Rx
Port
M
A Controller
#1
C
Tx
Rx
Tx
Port
M
Controller A
#5
C
Switch
Fabric
NI
NI
Rx
Port
M
A Controller
#2
C
Tx
Rx
Tx
NI
NI
Rx
Port
M
A Controller
#3
C
Rx
Tx
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Port
M
Controller A
#6
C
Tx
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M
Controller A
#7
C
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Verification methods
time
Artificial Test Vectors
(Generated Traffic)
Virtual Network
(Captured Traffic)
Current Position
Real-Traffic Based
(Real Traffic)
Target Stage
Hardware Emulation
(Real Traffic)
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Virtual Network
Virtual Network
Environment
Packets
to be sent
Vnet
I/F
Tx
Network
Processor(PLI)
Verilog
Simulator
MAC
interface
model
PC
SSRAM SDRAM
Packets
received
Vnet
I/F
Rx
SF
MAC
interface
model
PC
SSRAM SDRAM
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Virtual vs. Real-Traffic Based
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Captured packets vs. Raw packets
Analysis & Filtering vs. No pre-operation
Possible miss of some complicated case in virtual network
Faster simulation time due to cycle based verilog simulator in
real-traffic based
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Testbed for Real-Traffic Based Verification
Windows
Network
Processor(PLI)
Verilog
Simulator
Real
Network
Environment
MAC
(NIC)
MAC
interface
(PLI)
PC
SSRAM SDRAM
MAC
(NIC)
SF
MAC
interface
(PLI)
PC
SSRAM SDRAM
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Introduction to VCS
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Verilog Compiled Simulator
Fully-featured implementation of the standard Verilog
language(IEEE 1364)
Compiles Verilog source into executable object files
Faster than other interpretive Verilog simulator
Economical memory usage
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Introduction to VCS (cont’d)
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Compiling designs
VCS Compilation
no
-gen_asm
or –gen_c
yes
Verilog to assembly
or C source files
Verilog to object
files
Assemble or
Compile source files
into object files
Link object files into an
executable binary
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Introduction to VCS (cont’d)
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Incremental Compilation
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Triggering Recompilation
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Communicate the reason it recompiled a module
Shared Incremental Compile
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Recompile only those parts of the design that have changed
For multiple users
Compile-Time Options
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Large amount of options in compile time
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Current status[1]
Windows
Verilog
Simulator
Real
Network
Environment
MAC
(NIC)
Not prepared yet
MAC
(NIC)
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Current status[2]
Network
Environment
Switching Machine
- Simple bridging
- Negligible delay
Host Machine
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Next Presentation
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10/12 : simple packet forwarding and filtering through verilog
simulator
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