Transcript Universal Internet Measurement System for High Energy Physics

Universal Measurement
System with Web Interface
Maciej Lipiński
Ph.D. Krzysztof Poźniak, MSc Grzegorz Kasprowicz
Wilga 30.05.2008 r.
Presentation plan
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Outline of the project hardware
Goal and applications of the system
Characteristic of developed parts
Overview and details of system
interfaces
Future work
Outline of the project
Hardware provided by Grzegorz Kasprowicz, consists of 3
modules:
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Main module (100x80mm ):
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Single Board Computer module (50x70mm):
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Switched-mode Power Supply
Graphic controller
Sound controller
I2C interface
Peripherals: USB, RS232, Ethernet ports, output for
built-in LCD-TFT and for VGA monitor
Microprocessor: ARM9 (AT91RM9200)
128MB SDRAM
Ethernet interface 10/100 Mbit
FLASH 8MB
SD/MMC reader,
Interfaces: 2 x Serial ports, 2x USB hub and device
Acquisition module:
• ALTERA Cyclone I
• 2 x fast, 105MS/s. 14 bit ADCs
• SSRAM – 128k x 32
The goal of the project
Utilization of the hardware to create an autonomous,
universal measurement system with Ethernet interface and
operating system on board, in order to enable on-fly
reconfiguration accordingly to the user’s needs. Creation of
TCP/IP and web-based control interface.
Digital oscilloscope
Acquisition in
dangerous places
(i.e. high energy
physics)
Acquisition in
places which
are difficult to
access
Reconfigurable
measurement
system
Measurement system block diagram
and data flow
Universal Internet Measurement
System for High Energy Physics
Main Module
User interface
Ethernet
Measurement interface
External monitor
Single Board
Computer
ARM
Graphic
Acquisition
module
FPGA
LCD
ADC
Signal Source
S
S
R
A
M
Characteristics:
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Linux customized for AT91RM9200 :
• Kernel: linux-2.6.22.10
• Busybox: version 1.7.2
• uClibc library: version 0.9.29
FPGA configuration
• Done via SPI
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Acquisition logic features:
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Autotrigger and external trigger
Trigger slope choice
Sampling time
Trigger delay
Record lenght
Interrupt end of acquisition notification
Overview of interfaces
AT91RM9200
User’s space application for loading the FPGA configuration
User’s space application for acquisition control
Linux User Space
At91_spidev
open
/dev/spi
open
map
write
/dev/mem
read
Binary file with FPGA
configuration
open write
Data stored in
files
map
/dev/mem
/dev/mem
Linux File System
Configuration
registers
Static Memory
Controller (SMC)
Mapped external
memory
Linux Kernel
Space
spi_transfer
Linux User Space
Kernel Interface
Functions
map
External Bus Interface (EBI)
SPI
PIO A
PB1
PB2
MOSI
SPCK
Paraller Input/Output Controller (PIO)
D[15:0]
NSC0
NOE
NWR0
NWR1
A[15:0]
NWAIT
ADSC
CONF_DONE
nCONFIG
DCLK
DATA
ALTERA
CYCLONE I
Output parameter
registers
Input parameter
registers
Read/write controller
and
address decoder
OE
BWE
BW1
BW2
CE
SSRAM
CLK
Address[18:0]
Control register
ADC_SEL
ADC
ADC2[13:0]
Readout register
ADC1[13:0]
Status register
ADC
FPGA configuration design
AT91RM9200
User’s space application for loading the FPGA configuration
At91_spidev
open read
open write
map
/dev/spi
/dev/mem
Binary file with FPGA
configuration
Linux User Space
Linux User Space
Kernel Interface
Functions
Linux File System
Linux Kernel
Space
spi_transfer
SPI
PIO A
PB1
CONF_DONE
DCLK
nCONFIG
SPCK
DATA
PB2
MOSI
ALTERA
CYCLONE I
Acquired data readout
AT91RM9200
User’s space application for acquisition control
open write
Data stored in
files
Linux User Space
Linux User Space
Kernel Interface
Functions
map
map
/dev/mem
/dev/mem
Linux File System
Configuration
registers
Static Memory
Controller (SMC)
Mapped external
memory
External Bus Interface (EBI)
Paraller Input/Output Controller (PIO)
D[15:0]
NSC0
NOE
NWR0
NWR1
Input parameter
registers
A[15:0]
NWAIT
Output parameter
registers
Read/write controller
and
address decoder
Readout register
Control register
Status register
ALTERA CYCLONE I
Acquisition data storage
ADSC
Output parameter
registers
Input parameter
registers
Read/write controller
and
address decoder
OE
BWE
BW1
BW2
CE
SSRAM
CLK
Address[18:0]
Readout register
Control register
ADC_SEL
ADC
ADC2[13:0]
Status register
ADC1[13:0]
ALTERA
CYCLONE I
ADC
Work to be done:
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Research
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Peripheral drivers
Signal processing algorithms
Protocols
Visualization techniques
Interface management
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Bootable from SD/USB
Development of drivers
Appropriate components (ex. necessary server)
Reasonable size
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Signal processing algorithms implementation
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Programs (or drivers) development :
Operating System preparation
FPGA (HDL, glue logic)
Software
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Implementation of one of the standard measurement protocols
Create user interface:
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Tests
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Data processing
Data visualization
General configuration and reconfiguration
Remote application control
Remote measurement
Direct control (LCD, mouse, Keyboard)
The system will be tested as a double channel digital oscilloscope and
spectrum analyzer
The End