Transcript RSP 2000

Embedded System Architecture Design
Based on Real-Time Emulation
Carsten Nitsch, Udo
Kebschull
Institute of Computer Science
University of Leipzig
Karlheinz Weiß, Thorsten
Steckstor,
Wolfgang Rosenstiel
Embedded System Design Group
Forschungszentrum Informatik Karlsruhe
Overview

State of the Art
 Hardware First Approach
 Hardware/Software Co-Design

Emulation Based Methodology
 The Approach as a Two–Stage-Design Flow
 The Spyder tool set

Results and Experiences

Future Work: Distributed Emulation Environment
Carsten Nitsch
University of Leipzig
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Hardware First Approach
design time
start
1
specification
specification
Most commonly applied methodology:
partitioning into
intoHW
HWand
andSW
SW
partitioning
Partitioning mostly based on developer‘s
experience and intuition
Software design starts after complete
hardware implementation
2
mile
stones
3
HW-architecture
HW-architecture
design delay
implementation
implementation
4
SW-architecture
SW-architecture
5
implementation
implementation
6
integration&& test
test
integration
end
Major Disadvantages:
• Risk of design faults: System can not be tested at an early state
• Design delay between hardware and software design
Carsten Nitsch
University of Leipzig
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7
Hardware / Software Co-Design
Specification tries to build a complete
description of the system‘s behavior
Algorithm based concept
Verification of system design at an
early state in the design flow
Problems:
Insufficient knowledge about functional behavior of IP-cores
No unrestricted substitution of HW/SW components for real applications (few degrees of freedom for
micro controllers)
Carsten Nitsch
University of Leipzig
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Conclusion about these approaches
Problems:
 Hardware first approach:
 No Verification of the system design at an early stage of the design flow
process
 HW/SW Co-Design:
 limited by insufficient knowledge about internal behavior of IP - cores
 Restricted degrees of freedom
Both methodologies are unsuitable for developing embedded systems
consisting of only a few, but highly complex components.
Carsten Nitsch
University of Leipzig
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New: Emulation Based Methodology
Stage 1: System Design by Evaluation
Functional Specification
Not restricted to well-known
components
Initial Partitioning and pre-selection
Components analyzed by criteria like
functionality, complexity, or testability
Stage One: Evaluation
Source for these criteria: Data
sheets, manuals, ...
Stage Two:
Emulation
Stage Two:
Emulation
Stage 2: Validation by Emulation
no
Stage one influenced by knowledge
and
experience of the system
designer
validation avoids fatal design errors
Carsten Nitsch
University of Leipzig
pass ?
yes
pass ?
no
yes
System Integration and Test
K. Weiß: Architekturentwurf und Emulation eingebetteter Systeme.
Ph-D. Thesis, University of Tübingen 15.Oktober 1999
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Stage One: Evaluation
Decision-Making Criteria and Ranking:
Micro controller is most important
component (only a few types available)
determines basics like bus interface,
power supply, etc
Example Bus Interface:
Best case: complete compatibility of the busses of
the Microcontroller and component
Worst case: Highly complex bridges are necessary
construct a ranking system to choose the most suitable component
Carsten Nitsch
University of Leipzig
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Stage Two: Validation by Emulation
Spyder Virtex X2:
Designed for emulating
application specific
hardware or testing
IP-Cores
Spyder Core P2:
Designed for emulating
software components in a
real time environment
(VxWorks ready)
Carsten Nitsch
University of Leipzig
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Spyder-Virtex-X2
SPYDER-VIRTEX-X2/XCV300..800
Carsten Nitsch
University of Leipzig
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Spyder-Virtex-X2
arbiter
external
FPGA
configuratio
n header
serial EEPROMs 6 x
1Mbit
SSRAM
256k x 32
or
SDRAM
4M x 32
CPLD
XC95144xl
configuration
C-API-Routines for NT 4.0
Xilinx-Virtex-FPGA
PCI-interface
30
I
XCV300...XCV800
PLX-PCI9080
86
32
II
BGA 432
microcontroller
PCI - SLOT
86
connection to CORE-tools
power supply
+ 2,5V / 10A
+ 3,3V / 3A
Carsten Nitsch
University of Leipzig
SSRAM
256k x 32
or
SDRAM
4M x 32
extension header I and II
high density
logic analyzer connectors
10
Spyder-Core-P2/SH3
Carsten Nitsch
University of Leipzig
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Spyder-Core-P2
high density
RTOS: VxWorks
logic analyzer connectors
16MB SDRAM
SH3
7709A or
7729-DSP
133/66 MHz
BSP: TCP/IP,
RS232, Flash
EMBEDDED-BIOS
HDI monitor
GNU-C environment
CPLD
Buffer
EPROM
1Mx8
Flash
1 M x 32
CAN
10Base2
Ethernet
Extension
headers
JTAG
SER 0:2
86
connection to
FPGA-tools
86
Carsten Nitsch
University of Leipzig
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Experiences
Automotive Industries: Porting the VxWorks RTOS
Hardware First Approach:
Emulation Based Methodology:
Complex hardware prototype:
Emulation platform Spyder:
Multiple points of failure
Hardware tested
Limited debugging facilities
Good debugging facilities
Significant design delays
Comfortable developing environment
Using the Spyder System, it was possible to port VxWorks within
two weeks
Carsten Nitsch
University of Leipzig
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Future Work: Spyder - Virtex -X3
Scalable Emulation System Works in standalone mode:
uses TCP/IP for configuration and
communication:
VxWorks based firmware (Hitachi
SH3 architecture)
Appears as a black box to the user
Internet technology enables a virtual distributed laboratory.
Carsten Nitsch
University of Leipzig
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The Distributed Laboratory
Situation
Different know-how of the parties working
together
Developers only know a part of the whole
design
Communication between experts is very time consuming.
Approach: „transparent“ administration / upgrade via the internet
Carsten Nitsch
University of Leipzig
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The Distributed Laboratory
Example:
One team designs a hardware IPCore component
The IP-Core is stored at SpyderVirtex-X3 at a local file system
System integrators can use this
component
Flash Memory
SDRAM
Ethernet
File System
File System
TCP/ IP
Application
FPGA Driver
FPGA
Software Architecture of Spyder-Virtex-X3
The hardware designer group can upgrade the IP-Core design via internet
(Bug Fix on Demand)
C. Nitsch, U.Kebschull: Rekonfiguration zur Laufzeit
unter VxWorks, AES 2000, Karlsruhe
Carsten Nitsch
University of Leipzig
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The Distributed Laboratory
FTP Based Interface:
Modified FTP Server
“Special Directories”
System independent
Spyder-Virtex-X3 can be managed remotely.
Carsten Nitsch
University of Leipzig
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