Transcript Smart Dust Proposal Input - University of Maryland

Digital Processing Platform
 Low power design and implementation of computation associated
with protocols and fusion algorithms
 Low power micro-controller
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Small size for compact integration
Enables adaptation of node behavior with changing requirements,
environmental characteristics, and network state
 Enables experimentation with different algorithms and protocols
 Enables use of energy saving processor modes and associated
operating system functionality
 Development of streamlined software implementations
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Highly memory-constrained software implementations are required due
to size and energy constraints
Must handle streaming nature of input data
Leverage our previous work in synthesis of memory-efficient embedded
software implementations
Employ formal programming models, and apply graph-theoretic analysis
and optimization of program structure
Explore migration into ASIC or 3D-integrated system
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Smart Dust Digital Processing, 1
Example of Software Structure
Receiver
No new data
Low power
sleep mode
Periodic wake-up
Check for
new data
Sensor
Transmitter
No
Broadcast
new data
Yes
Extract data
Need to
update
neighbors?
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Fuse with
prior data
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Protocol Set-up and System Configuration
 Handshaking
 Source channel coding
 Integrate with transceiver to establish PLL timing
 Establish error correction coding
 Establish low-complexity decoding
 Assign transmission power
 Assign processing tasks to network nodes
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Smart Dust Digital Processing, 3
System-level Optimization Example:
Task Assignment Algorithms
 Need to balance communication and computation
throughout the network
 Develop models of power consumption in network nodes
and communication links
 Develop task graph models of overall network
functionality
 Develop algorithms to embed task graph algorithm
specifications into the network
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Assign processing tasks to network nodes
Turn off idle nodes
Large design space
 Explore evolutionary algorithms to optimize task graph
embeddings
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Smart Dust Digital Processing, 4
Evolutionary Algorithms
Selection
Phenotype space
(Original search space)
P(t+1)
P(t)
Decoding function
Genetic
operators
Genotype space
(Genetic representation)
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G(t+1)
G(t)
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Digital Design Summary
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Contributions
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Low power, memory-constrained implementation techniques
 Application-specific optimization of software and VLSI
 Integrated optimization of protocols and system configuration
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Selected Prior Work
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N. K. Bambha, S. S. Bhattacharyya, J. Teich, and E. Zitzler. Systematic integration
of parameterized local search in evolutionary algorithms. IEEE Transactions on
Evolutionary Computation. To appear.
 S. S. Bhattacharyya. Hardware/software co-synthesis of DSP systems. In Y. H. Hu,
editor, Programmable Digital Signal Processors: Architecture, Programming, and
Applications, pages 333-378. Marcel Dekker, Inc., 2002.
 P. K. Murthy and S. S. Bhattacharyya. Shared buffer implementations of signal
processing systems using lifetime analysis techniques. IEEE Transactions on
Computer-Aided Design of Integrated Circuits and Systems, 20(2):177-198,
February 2001.
 S. S. Bhattacharyya, R. Leupers, and P. Marwedel. Software synthesis and code
generation for DSP. IEEE Transactions on Circuits and Systems --- II: Analog and
Digital Signal Processing, 47(9):849-875, September 2000.
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Smart Dust Digital Processing, 6