Transcript JFET DC Biasing - Brookdale Community College, Lincroft

JFET Biasing
ELEC 121
JFET Fixed Bias
VGG + IGRG + VGS = 0
Since IG = 0
VGS = - VGG
RG is present to limit current
in case VGG is connected
with wrong polarity
This would forward bias the
gate-source junction causing
high currents, which would
destroy the transistor
Since GS is
reverse biased, IG
= 0 and VRG = 0
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DC Analysis for JFET Fixed Bias Network
VGS 

ID = IDSS  1 
VP 

2
VGS = - VGG
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JFET Fixed Bias Plotting Shockley’s Equation
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JFET Fixed Bias Graphical Solution
VGS 

ID = IDSS  1 
V
P


2
Since VGS = - VGG
VGG 

ID = IDSS  1 
V
P


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JFET Fixed Bias
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Graphical Solution for JFET Fixed Bias
VGS 

ID = IDSS  1 
VP 

2
VGG 

ID = IDSS  1 
VP 

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JFET Self Bias Configuration
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JFET Self Bias DC Equivalent Circuit
IG = 0
VRG = 0
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Transconductance Curve
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JFET Self Bias Load Line
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JFET Self Bias
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JFET Self Bias Transconductance Curve
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Graphical Solution of JFET Self Bias
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JFET Self Bias Effect on Variation of RS
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Self Bias
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JFET Voltage Divider Bias
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JFET Voltage Divider Bias DC Analysis
Input
 R2 
VG = VDD 

R
1
+
R
2


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Output
-VG + IDRG + VGS + IDRS = 0
VGS = VG - IDRS
ELEC 121
VDS = VDD - ID (RD + RS)
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JFET Voltage Divider Bias Load Line
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The Effect of RS on Q-point
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JFET Voltage Divider Bias
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JFET Voltage Divider Bias Q-point
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Voltage Divider Bias
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JFET Self Bias with Dual Supply
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Determination of Q-point for Self Bias with Dual Supply
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Common Gate JFET Self Bias
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Common Gate JFET Self Bias DC Bias Circuit
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Common Gate JFET Self Bias
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