Transcript EE24C Digital Electronics Project

EE24C Digital Electronics Project
Design of a Digital Alarm Clock
Sept. 2005
EE24C Digital Electronics Project
Contents
•
•
•
•
Natural Specification
Design Specification
Labs Description
Theory :
– Sequential Logic Design
– Counters and Registers
• Design Solution
• Material Resources
Sept. 2005
EE24C Digital Electronics Project
Natural Specification
(From a Hardware Store Owner)
"I’m proposing a 2-month contract to a second year
Electrical and Computer Eng. student. The elected
student will have to develop for the local market a digital
clock that displays time, i.e. 2:00:00 AM. The device
should have features such as time setting, alarm setting,
autonomy of 3 hours in case of power failure, and proper
time display using 7-segment Leds."
Sept. 2005
EE24C Digital Electronics Project
From the previous specification, a good design approach consists of
analyzing the system in terms of its functionality(block diagrams) and
electrical properties.
For this design we will use an FPGA board as the target architecture
and Xiinx ISE/Modelsim as the software development platform.
We consider the following steps which are crucial for the project
completion:
• Modular analysis and implementation of the system.
• Analysis of electrical properties (power consumption, operating
frequency, size on chip).
• Implementation and testing of the final design.
• Writing of a small user manual to be included in your project report.
Sept. 2005
EE24C Digital Electronics Project
Design Specification
The system is synchronous and reactive1. It uses a reference clock of 50
MHz in order to generate other useful signals for its internal operations.
We can identify four major functions:
• Commands entering via a 4 x 3 keypad which is used for setting
purposes.
• Counting module made of four BCD counters which modulo are 2,
12(counting from 1 to 11), 60, and 60 respectively.
• FSM controller that is used for the sequencing of events.
• Time-multiplexing display of the correct time (i.e 2:30:58 am).
Sept. 2005
EE24C Digital Electronics Project
Figure 1: Block diagram of the digital alarm clock
DisplayUnit made of 7-segment Leds and 4 normal Leds, time format: 2:00:10 AM
7-bit segment code
MultiplexingSeg[6:0]
Clk
7-bit anode
selection
Leds[3:0]
Anode[6:0]
Disp_h[7:0]
Disp_m[7:0]
8 bits (2 BCDs)
1 Hz
areset
Time-Multiplexing Display decoder module
Disp_ap
Dout
4-bit LEDs for :
Disp_s[7:0]
8 bits (2 BCDs)
8 bits (2 BCDs)
cp
Tch Douth[8:0] cp
Tcm Doutm[8:0] cp
Counter AM/PM
Mod-2
Clock st ce
clr Din0
Counters of Hours
Mod-12
st ce clr Din[8:0]
Counter of Minutes
Mod-60
st ce clr Din[8:0]
Counter of Seconds
Mod-60
st ce clr Din[8:0]
Reset
Reset
Reset
st_ap CE
st_h CE
st_m CE
Reset
Tcs Douts[8:0]
st_s CE
al_clk
8-bit time value
(2 BCDs)
Control Module + ALARM settings
17-bit Count
ctr_clk
cnt_code[1:0] st_cnt st_alr clr_sig Data_alr[15:0]
ct_clk
Reset
al_clk
Ccode[1:0]
st_c
st_al
Keycode[16:0]
db_clk
Debounce-free Keypad Encoder
Reset
Reference clock
Sept. 2005
Alarm pulse that
activates the buzzer
17-bit Alarm
Code
EE24C Digital Electronics Project
Key_signal[11:0]
Frequency
Divider
db_clk
mux_clk
2-bit Counter Code
4x3 Keypad
12-bit
Code
Figure 2: Controller and alarm modules
Alarm Code
2
clr_sig
st_alr
ctr_clk
cnt_code[1:0]
Data_alr[15:0]
ld_alarm
Pulse to Buzzer
load
Alarm
Controller
17 bits
st_ap
st_h
st_m
st_s
clr
CE
reset
Sept. 2005
EE24C Digital Electronics Project
ctr_clk
al_clk
al_dis
( Am/Pm, Hour & Mn Code)
st_cnt
17 bits
Alarm Code
17 bits
ctr_clk
load
Data_alr
17-bit Alarm
Register
17-bit count (Am/Pm, Hours & Minutes)
clr
Data_out
17 bits
17 bits
Figure 3: Alarm
module
A[16:0]
B[16:0]
17-bit Comparator
equal
60 s
al_dis
To the Buzzer
al_clk (Alarm pulse)
Sept. 2005
EE24C Digital Electronics Project
- Lab 1: Design of Modulo counters
- Lab 2: Debounce-free Keypad Encoder and Time-multiplexing Display
Decoder
- Lab 3 Frequency Divider and Alarm Module
- Lab 4: Buzzer module and Power Failure Detection
- Lab 5: FSM Controller Module
- Project Realization: Integration and Testing
Sept. 2005
EE24C Digital Electronics Project
Lab 1: Design of Modulo Counters
Sept. 2005
EE24C Digital Electronics Project
Basic element to be used
Sept. 2005
EE24C Digital Electronics Project
Sept. 2005
EE24C Digital Electronics Project
Sept. 2005
EE24C Digital Electronics Project
8 bits
Dout
`
8 bits
Doutm[7:0]
Douth[7:0]
8 bits
Douts[7:0]
ct-clk
Counting Module (Am/Pm, Hours, Minutes, and Seconds)
st_ap
CE
clr
st_h
Figure 7: Counting Module’s Block Diagram
Sept. 2005
EE24C Digital Electronics Project
st_m
st_s
Lab 2: Keypad Encoder and Time-multiplexing
Display Decoder
Debounce-free Keypad Encoder
Sept. 2005
EE24C Digital Electronics Project
Sept. 2005
EE24C Digital Electronics Project