CBT Project on VLSI Design 2001

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Transcript CBT Project on VLSI Design 2001 

VLSI Design
Third Year Standard Project - SB1
Second Mini Lecture
Web page:
https://camtools.cam.ac.uk
David M Holburn
David Chuah
Jiming Jiang
12th May - 6th June 2009
Cambridge University
Engineering Department
Summary of progress so far
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Engineering Department
Developed ring oscillator (RO) concept
Confirmed using VHDL & ModelSim
Explored effect of varying NOR delays (ModelSim)
Built symbol & schematic
Used QuickSimII to predict timing characteristics
of RO using Mietec NOR2 design
Examined & edited transistor level schematic for a
simple 2-input NOR gate
Investigated characteristics of real RO design using
oscilloscope/counter
Labs 6 & 7
Lab Guide 6
 Gain familiarity with layout and ICgraph layout editor
 Adapt mask layouts for the 2-input NOR gate nor2
 Identify/correct design rule violations in nor2 layout
 Print out layout plot for your nor2 layout design
Lab Guide 7
 Verification - check for proper correspondence between your
nor2 layout & the nor2t transistor schematic
 Investigate effect of parasitic elements C and R in layout
 Simulate the results using AccuSim
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The fabricated ring oscillator
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Layout and stick diagrams
p and n-type
MOSFET
channels
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MOSFET channels
and interconnect
Interconnect,
channels and
gate electrodes
Layout and stick diagrams (2)
Contact
(black)
Polysilicon
(red)
Metal
(blue)
P-active
(orange)
N-active
(green)
Input
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Contact cuts
(one of four)
Output
Form Factor
Identical logic functions
Channels aligned horizontally
Short, wide form factor
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Channels aligned vertically
Tall, thin form factor
Stick diagrams: NAND
VDD
Input A
D
S
D
S
Input B
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Output
VSS
Stick diagrams: NOR
Output in polySi
crosses under VDD
Input B
VDD
NB: contact cut
links m1 and poly
Output
wired in metal 1
Input A
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VSS
Design rules
Mask 40 : Poly 1
4A Minimum poly 1 width
3m
Current density must not exceed 160A/m
4B Minimum Gate length
(3m)
4C Minimum Poly 1 spacing or notch width
3m
4D Minimum Poly 1 to Diffusion spacing 1.5m
4E Mimimum Poly 1 extension on field oxide
2.5m
4F Mimimum source and drain width
4m
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Lab Guide 6 - layout of nor2t
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ICgraph operations
– familiarise with basic
techniques
– study & understand layout
– detect
& correct
rule violations
add gate
electrodes
– connect output
– consider how to optimise layout
» size
» speed
» convenience of
input/output
» compatible with other cells
– plot completed layout
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Link
Accusim - for detailed simulation
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DC characteristic for nor2t
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Transient performance of nor2t
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Parasitic capacitances in nor2t
A
B
Y
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Capacitances due to
interconnect
Mietec CMOS24 Technology - Interconnect specific capacitances
Material
Specific
capacitance
to substrate
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Polysilicon
4.03  10-2
Metal1
2.3  10-2
Metal2
1.73  10-2
Units
fF m-2
[1fF = 10-15 F]
Wiring parasitics
A
A
Y
B
A
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Y
B
B
Y
A
B
Y
Response with all parasitics
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Final week - Semi Custom
Design
Lab Guide 8
 Use ICgraph, ICplan, ICblocks & ICcompact
 Create complete layout for ring oscillator design
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Automatic and interactive floor-planning
Automatic cell placement
Automatic routing of interconnect
Minimisation of vias
Compaction of design
Flattened and Hierarchical designs
Generate colour check plot of result
Flattened layout top_level_flat
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Via minimisation
After Via Minimisation
BeforeVia Minimisation
Metal 2
Metal 2
Metal 1
Metal 1
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Metal 1
Metal 1
Hierarchical layout design
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Hierarchy - a methodology for creating larger
design from smaller design objects
At lowest level objects are polygons, shapes
and paths (leaf cells), e.g. nor2, nand2
Inserted in a multi-tiered, hierarchical design
Designer controls visibility of detail
Allows construction of libraries of commonly
used parts e.g. ring_count (based on counter4)
Permits re-use of designs in other projects
Hierarchical Objects
fs_comparator
fs_divider
ring_oscillator
fs_control
ring_glue
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Create fs_divider layout cell
fs_divider
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Possible schematic for
fs_divider
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Floor plan for fs_divider
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Place standard cells
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Autoroute interconnect
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Auto-placement for
ring_oscillator
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Completed routing in
ring_oscillator
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Placement for ring_glue
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Completed routing for ring_glue
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Floor plan for top_level_hier
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Unplaced cells
2 input pad cells
(marked ‘E’)
unplaced because
there was
insufficient space
around periphery
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Editing the floor plan
Using the
Edit >
Stretch
command to
reshape the
floorplan
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Successful placement
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After routing top_level_hier
Yellow lines small number
of
connections
which could
not be routed
by ICblocks these must be
hand-routed
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Completed layout
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After compaction
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