Transcript No Slide Title

Non Volatile
MEMORIES
Elettronica T AA 2010-2011
Memory
Digital Integrated Circuits © Prentice Hall 2003
Chapter Overview
• Memory Classification
• Memory Architectures
• The Memory Core
• Periphery
• Reliability
Elettronica T AA 2010-2011
Memory
Digital Integrated Circuits © Prentice Hall 2003
Semiconductor Memory
Classification
RWM
Random
Access
Non-Random
Access
SRAM
FIFO
DRAM
LIFO
NVRWM
ROM
EPROM
Mask-Programmed
E2PROM
Programmable (PROM)
FLASH
Shift Register
CAM
Elettronica T AA 2010-2011
Memory
Digital Integrated Circuits © Prentice Hall 2003
Memory Architecture: Decoders
Elettronica T AA 2010-2011
Memory
Digital Integrated Circuits © Prentice Hall 2003
Array-Structured Memory Architecture
Problem: ASPECT RATIO or HEIGHT >> WIDTH
AK
AK+1
AL-1
Bit Line
Storage Cell
Row Decoder
2L-K
Word Line
M.2K
Sense Amplifiers / Drivers
A0
Column Decoder
AK -1
Amplify swing to
rail-to-rail amplitude
Selects appropriate
word
Input-Output
(M bits)
Elettronica T AA 2010-2011
Memory
Digital Integrated Circuits © Prentice Hall 2003
MOS NOR ROM
VDD
Pull-up devices
WL[0]
GND
WL[1]
WL[2]
GND
WL[3]
BL[0]
Elettronica T AA 2010-2011
BL[1]
Memory
BL[2]
BL[3]
Digital Integrated Circuits © Prentice Hall 2003
MOS NAND ROM
V DD
Pull-up devices
BL[0]
BL[1]
BL[2]
BL[3]
WL[0]
WL[1]
WL[2]
WL[3]
All word lines high by default with exception of selected row
Elettronica T AA 2010-2011
Memory
Digital Integrated Circuits © Prentice Hall 2003
Precharged MOS NOR ROM
VDD
 pre
Precharge devices
WL[0]
GND
WL[1]
WL[2]
GND
WL[3]
BL[0] BL[1]
BL[2] BL[3]
PMOS precharge device can be made as large as necessary,
but clock driver becomes harder to design.
Elettronica T AA 2010-2011
Memory
Digital Integrated Circuits © Prentice Hall 2003
Floating-gate transistor (FAMOS)
Floating gate
Gate
D
Drain
Source
tox
G
tox
p
n+
n+
S
Substrate
(a) Device cross-section
Elettronica T AA 2010-2011
Memory
(b) Schematic symbol
Digital Integrated Circuits © Prentice Hall 2003
Floating-Gate Transistor Programming
20 V
0V
20 V
10 V 5 V
S
D
Avalanche injection.
Elettronica T AA 2010-2011
5 V
S
5V
0V
2.5 V
S
D
Removing programming voltage
leaves charge trapped.
Memory
5V
D
Programming results in
higher V T.
Digital Integrated Circuits © Prentice Hall 2003
FLOTOX EEPROM
Floating gate
I
Gate
Drain
Source
VGD
10 V
20-30 nm
10 V
n+
n+
Substrate
p
10 nm
(a) Flotox transistor
(b) Fowler-Nordheim I-V characteristic
BL
WL
V DD
(c) EEPROM cell during a read operation
Elettronica T AA 2010-2011
Memory
Digital Integrated Circuits © Prentice Hall 2003
Flash EEPROM
Control gate
Floating gate
Thin tunneling oxide
erasure
n+ source
programming
n+ drain
p-substrate
Elettronica T AA 2010-2011
Memory
Digital Integrated Circuits © Prentice Hall 2003
Cross-sections of NVM cells
Flash
Elettronica T AA 2010-2011
Courtesy Intel
Memory
EPROM
Digital Integrated Circuits © Prentice Hall 2003
Characteristics of State-of-the-art
NVM
Elettronica T AA 2010-2011
Memory
Digital Integrated Circuits © Prentice Hall 2003