Transcript Document

Memory (Contd..)
ETEG 431
SG
Memory Timing: Definitions
Memory
ETEG 431
SG
Semiconductor Memory Classification
Read-Write Memory
Non-Volatile
Read-Write
Read-Only Memory
Memory
Random
Access
Non-Random
Access
EPROM
2
E PROM
SRAM
FIFO
DRAM
LIFO
Shift Register
CAM
Mask-Programmed
FLASH
Programmable (PROM)
Memory
ETEG 431
SG
Read-Only Memory Cells
BL
BL
BL
VDD
WL
WL
WL
1
BL
WL
BL
BL
WL
WL
0
GND
Diode ROM
MOS ROM 1
MOS ROM 2
Memory
ETEG 431
SG
MOS OR ROM
BL[0]
BL[1]
BL[2]
BL[3]
WL[0]
V DD
WL[1]
WL[2]
V DD
WL[3]
V bias
Pull-down loads
Memory
ETEG 431
SG
EPROM: Floating-Gate Transistor Programming
20 V
0V
20 V
S
D
Avalanche injection
5V
0V
S
D
Removing programming
voltage leaves charge trapped
5V
S
D
Programming results in
higher V T .
Memory
ETEG 431
SG
EEPROM
Gate
Floating gate
Drain
Source
WL
20–30 nm
n1
n1
Substrate
p
10 nm
VDD
Memory
ETEG 431
SG
Flash EEPROM
Control gate
Floating gate
erasure
n 1 source
Thin tunneling oxide
programming
p-substrate
n 1 drain