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SEMICONDUCTOR
MEMORIES
Digital Integrated Circuits
Memory
© Prentice Hall 1995
Chapter Overview
• Memory Classification
• Memory Architectures
• The Memory Core
• Periphery
• Reliability
Digital Integrated Circuits
Memory
© Prentice Hall 1995
Semiconductor Memory
Classification
RWM
Random
Access
Non-Random
Access
SRAM
FIFO
DRAM
LIFO
NVRWM
ROM
EPROM
Mask-Programmed
E2PROM
Programmable (PROM)
FLASH
Shift Register
CAM
Digital Integrated Circuits
Memory
© Prentice Hall 1995
Memory Architecture: Decoders
Digital Integrated Circuits
Memory
© Prentice Hall 1995
Array-Structured Memory Architecture
Problem: ASPECT RATIO or HEIGHT >> WIDTH
AK
AK+1
AL-1
Bit Line
Storage Cell
Row Decoder
2L-K
Word Line
M.2K
Sense Amplifiers / Drivers
A0
Column Decoder
AK -1
Amplify swing to
rail-to-rail amplitude
Selects appropriate
word
Input-Output
(M bits)
Digital Integrated Circuits
Memory
© Prentice Hall 1995
Hierarchical Memory Architecture
Row
Address
Column
Address
Block
Address
Global Data Bus
Control
Circuitry
Block Selector
Global
Amplifier/Driver
I/O
Advantages:
1. Shorter wires within blocks
2. Block address activates only 1 block => power savings
Digital Integrated Circuits
Memory
© Prentice Hall 1995
MOS NOR ROM Layout
Metal1 on top of diffusion
WL[0]
GND (diffusion)
WL[1]
Polysilicon
Basic cell
10 x 7 
Metal1
WL[2]
2
WL[3]
Only 1 layer (contact mask) is used to program memory array
Programming of the memory can be delayed to one of
last process steps
Digital Integrated Circuits
Memory
© Prentice Hall 1995
MOS NOR ROM Layout
BL[0]
BL[1]
BL[2]
BL[3]
Threshold raising
implant
WL[0]
GND (diffusion)
Basic Cell
8.5 x 7 
Metal1 over diffusion
WL[1]
Polysilicon
WL[2]
WL[3]
Threshold raising implants disable transistors
Digital Integrated Circuits
Memory
© Prentice Hall 1995
MOS NAND ROM
V DD
Pull-up devices
BL[0]
BL[1]
BL[2]
BL[3]
WL[0]
WL[1]
WL[2]
WL[3]
All word lines high by default with exception of selected row
Digital Integrated Circuits
Memory
© Prentice Hall 1995
MOS NAND ROM Layout
Diffusion
Polysilicon
Basic cell
5x 6 
Threshold
lowering
implant
No contact to VDD or GND necessary;
drastically reduced cell size
Loss in performance compared to NOR ROM
Digital Integrated Circuits
Memory
© Prentice Hall 1995
Precharged MOS NOR ROM
VDD
 pre
Precharge devices
WL[0]
GND
WL[1]
WL[2]
GND
WL[3]
BL[0] BL[1]
BL[2] BL[3]
PMOS precharge device can be made as large as necessary,
but clock driver becomes harder to design.
Digital Integrated Circuits
Memory
© Prentice Hall 1995
Characteristics of State-of-the-art
NVM
Digital Integrated Circuits
Memory
© Prentice Hall 1995
Read-Write Memories (RAM)
• STATIC (SRAM)
Data stored as long as supply is applied
Large (6 transistors/cell)
Fast
Differential
• DYNAMIC (DRAM)
Periodic refresh required
Small (1-3 transistors/cell)
Slower
Single Ended
Digital Integrated Circuits
Memory
© Prentice Hall 1995
6-transistor CMOS SRAM Cell
WL
VDD
M2
M4
Q
M6
Q
M5
M1
M3
BL
Digital Integrated Circuits
BL
Memory
© Prentice Hall 1995
CMOS SRAM Analysis (Write)
WL
VDD
M4
Q=0
M6
Q=1
M5
M1
VDD
BL = 1
BL = 0
2
2
VDD VDD
VDD VDD
k n M6   VDD – VTn  ----------- – ----------  = k p M4  VDD – VTp  ----------- – ----------


2
2
8 
8 
kn M5 V
VDD 2
V DD V 2
DD
DD 
-------------- ---------- – V Tn  -----------  = kn  M1   VDD – VTn ----------- – ---------- 2 

2  2
2
8 
Digital Integrated Circuits
Memory
(W/L)n,M60.33 (W/L)p,M4
(W/L)n,M5 10 (W/L)n,M1
© Prentice Hall 1995
CMOS SRAM Analysis (Read)
WL
VDD
M4
BL
Q= 0
M6
M5
Q=1
M1
V DD
BL
V DD
V DD
Cbit
C bit
kn M5 V
VD D 2
VDD V 2
DD- – V  ----------D D- 
 V
--------------- -----------  = k
------------ – ----------–
V

Tn  2  
n M1  D D
Tn
2  2
2
8 
(W/L)n,M510 (W/L)n,M1
Digital Integrated Circuits
(supercedes read constraint)
Memory
© Prentice Hall 1995
6T-SRAM — Layout
M2
VDD
M4
Q
Q
M1
M3
GND
M5
M6
BL
Digital Integrated Circuits
Memory
WL
BL
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Resistance-load SRAM Cell
WL
VDD
RL
Q
RL
Q
M3
BL
M4
M1
M2
BL
Static power dissipation -- Want RL large
Bit lines precharged to VDD to address t p problem
Digital Integrated Circuits
Memory
© Prentice Hall 1995
3-Transistor DRAM Cell
BL1
BL2
WWL
WWL
RWL
RWL
M3
X
M1
X
M2
VDD -VT
BL1
VDD
BL2
VDD -VT
CS
V
No constraints on device ratios
Reads are non-destructive
Value stored at node X when writing a “1” = VWWL -VTn
Digital Integrated Circuits
Memory
© Prentice Hall 1995
3T-DRAM — Layout
BL2
BL1
GND
RWL
M3
M2
WWL
M1
Digital Integrated Circuits
Memory
© Prentice Hall 1995
1-Transistor DRAM Cell
BL
WL
Write "1"
Read "1"
WL
M1
X
CS
VDD VT
GND
VDD
BL
VDD/2
CBL
sensing
VDD /2
Write: CS is charged or discharged by asserting WL and BL.
Read: Charge redistribution takes places between bit line and storage capacitance
CS
 V = VBL – V PRE =  V BIT – V PRE  -----------------------C S + CBL
Voltage swing is small; typically around 250 mV.
Digital Integrated Circuits
Memory
© Prentice Hall 1995
DRAM Cell Observations
1T DRAM requires a sense amplifier for each bit line, due to
charge redistribution read-out.
DRAM memory cells are single ended in contrast to SRAM cells.
The read-out of the 1T DRAM cell is destructive; read and
refresh operations are necessary for correct operation.
Unlike 3T cell, 1T cell requires presence of an extra capacitance
that must be explicitly included in the design.
When writing a “1” into a DRAM cell, a threshold voltage is lost.
This charge loss can be circumvented by bootstrapping the
word lines to a higher value than VDD .
Digital Integrated Circuits
Memory
© Prentice Hall 1995
1-T DRAM Cell
Capacitor
Metal word line
M1 word
line
SiO2
poly
n+
Field Oxide
n+
poly
Inversion layer
induced by
plate bias
Diffused
bit line
Polysilicon
Polysilicon
plate
gate
(a) Cross-section
(b) Layout
Used Polysilicon-Diffusion Capacitance
Expensive in Area
Digital Integrated Circuits
Memory
© Prentice Hall 1995
Periphery
• Decoders
• Sense Amplifiers
• Input/Output Buffers
• Control / Timing Circuitry
Digital Integrated Circuits
Memory
© Prentice Hall 1995
Row Decoders
Collection of 2M complex logic gates
Organized in regular and dense fashion
(N)AND Decoder
NOR Decoder
Digital Integrated Circuits
Memory
© Prentice Hall 1995
Dynamic Decoders
Precharge devices
GND
GND
VDD
WL 3
WL 3
VDD
WL 2
VDD
WL 1
WL 2
WL 1
VDD
WL 0
V DD 
A0
A0
A1
A1
Dynamic 2-to-4 NOR decoder
WL 0
A0
A0
A1
A1

2-to-4 MOS dynamic NAND Decoder
Propagation delay is primary concern
Digital Integrated Circuits
Memory
© Prentice Hall 1995
A NAND decoder using 2-input predecoders
WL 1
WL 0
A0A1 A0 A1 A0 A1 A0A 1
A 2A3 A2 A3 A2 A3 A2 A3
A1 A 0
A3 A2
A0
A1
A2
A3
Splitting decoder into two or more logic layers
produces a faster and cheaper implementation
Digital Integrated Circuits
Memory
© Prentice Hall 1995
4 input pass-transistor based column
decoder
A0
A1
2 input NOR decoder
BL0
BL1
BL2
BL3
S0
S1
S2
S3
D
Advantage: speed (t pd does not add to overall memory access time)
only 1 extra transistor in signal path
Disadvantage: large transistor count
Digital Integrated Circuits
Memory
© Prentice Hall 1995
4-to-1 tree based column decoder
BL0
BL1
BL2
BL3
A0
A0
A1
A1
D
Number of devices drastically reduced
Delay increases quadratically with # of sections; prohibitive for large decoders
Solutions: buffers
progressive sizing
combination of tree and pass transistor approaches
Digital Integrated Circuits
Memory
© Prentice Hall 1995
Sense Amplifiers
make V as small
as possible
 V
tp = C
---------------Iav
large
small
Idea: Use Sense Amplifer
small
transition
s.a.
input
Digital Integrated Circuits
Memory
output
© Prentice Hall 1995
Differential Sensing - SRAM
VDD
VDD
PC
BL
VDD
EQ
VDD
y M3
BL
M1
x
SE
WLi
M4
M2
y
x x
x
M5
SE
(b) Doubled-ended Current Mirror Amplifier
VDD
SRAM cell i
y
Diff.
Sense
x
x
Amp
y
y
D
D
x
x
SE
(a) SRAM sensing scheme.
Digital Integrated Circuits
y
(c) Cross-Coupled Amplifier
Memory
© Prentice Hall 1995
Latch-Based Sense Amplifier
EQ
BL
BL
VDD
SE
SE
Initialized in its meta-stable point with EQ
Once adequate voltage gap created, sense amp enabled with SE
Positive feedback quickly forces output to a stable operating point.
Digital Integrated Circuits
Memory
© Prentice Hall 1995
Open bitline architecture
EQ
L1
R
L0
R0
R1
L
VDD
SE
BLL
CS
...
CS
BLR
CS
SE
dummy
cell
Digital Integrated Circuits
CS
...
CS
CS
dummy
cell
Memory
© Prentice Hall 1995
DRAM Read Process with Dummy Cell
V (Volt)
6.0
4.0
BL
2.0
BL
5.0
1
2
3
t (nsec)
(a) reading a zero
4
5
6.0
4.0
V (Volt)
0.00
SE
3.0
2.0
EQ
1.0
0.00
V (Volt)
WL
4.0
1
2
3
4
(c) control signals
5
BL
2.0
0.00
BL
1
2
3
t (nsec)
4
5
(b) reading a one
Digital Integrated Circuits
Memory
© Prentice Hall 1995
Programmable Logic Array
Product Terms
x 0x 1
x2
AND
PLANE
OR
PLANE
f0
x0
Digital Integrated Circuits
x1
f1
x2
Memory
© Prentice Hall 1995
Pseudo-Static PLA
GND
GND
GND
VD D
GND
GND
GND
GND
VDD
x0
x0
x1
x1
x2
AND-PLANE
Digital Integrated Circuits
x2
f0
f1
OR-PLANE
Memory
© Prentice Hall 1995
Dynamic PLA
 A ND
VDD
GND
 OR
O R
AND
VDD
x0
x0
x1
x1
x2
AND-PLANE
Digital Integrated Circuits
x2
f0
f1
GND
OR-PLANE
Memory
© Prentice Hall 1995
Clock Signal Generation
for self-timed dynamic PLA

 AND

Dummy AND Row
AND
AND
 OR
Dummy AND Row
OR
(a) Clock signals
Digital Integrated Circuits
(b) Timing generation circuitry.
Memory
© Prentice Hall 1995
PLA Layout
And-Plane
VDD
x0 x0 x1 x1 x2 x2
Pull-up devices
Digital Integrated Circuits
Memory
Or-Plane

GND
f0 f1
Pull-up devices
© Prentice Hall 1995
PLA versus ROM
Programmable Logic Array
structured approach to random logic
“two level logic implementation”
NOR-NOR (product of sums)
NAND-NAND (sum of products)
IDENTICAL TO ROM!
Main difference
ROM: fully populated
PLA: one element per minterm
Note: Importance of PLA’s has drastically reduced
1. slow
2. better software techniques (mutli-level logic
synthesis)
Digital Integrated Circuits
Memory
© Prentice Hall 1995
Semiconductor Memory Trends
Memory Size as a function of time: x 4 every three years
Digital Integrated Circuits
Memory
© Prentice Hall 1995
Semiconductor Memory Trends
Increasing die size
factor 1.5 per generation
Combined with reducing cell size
factor 2.6 per generation
Digital Integrated Circuits
Memory
© Prentice Hall 1995
Semiconductor Memory Trends
Technology feature size for different SRAM generations
Digital Integrated Circuits
Memory
© Prentice Hall 1995