Transcript Slide 1
Design and Implementation of VLSI Systems
(EN1600)
Lecture 29: Array Subsystems (SRAM)
Prof. Sherief Reda
Division of Engineering, Brown University
Spring 2008
[sources: Weste/Addison Wesley – Rabaey/Pearson]
S. Reda EN1600 SP’08
Array subsystems
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•
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SRAM
DRAM
ROM
FLASH
PLA/FPGA
S. Reda EN1600 SP’08
Array architecture
2m bits
S0
2m bits
S0
Word 0
S1
Word 1
S2
Word 2
words
N SN -
2
SN -
1
Storage
cell
Word 0
A0
Word 1
A1
Word 2
An -
1
Word N - 2
DecoderWord N - 2
Word N - 1
Word N - 1
Storage
cell
n = log2N
Input-Output
(M bits)
Intuitive architecture for N x 2m memory
Too many select signals:
N words == N select signals
Input-Output
(M bits)
Decoder reduces the number of select signals
n = log 2N
Problem: ASPECT RATIO
or HEIGHT >> WIDTH
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Array architecture
• 2n words of 2m bits each
• If n >> m, fold by 2k into fewer rows of more columns
wordlines
row decoder
2.
bitline conditioning
3.
1. core
n-k
k
n
3.
column
decoder
bitlines
memory cells:
2n-k rows x
2m+k columns
column
circuitry
2m bits
• Good regularity – easy to design
• Very high density if good cells are used
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1. Core. 12T SRAM Cell
• Basic building block: SRAM Cell
– Holds one bit of information, like a latch
– Must be read and written
• 12-transistor (12T) SRAM cell
– Use a simple latch connected to bitline
– 46 x 75 λ unit cell
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6T SRAM Cell
• Cell size accounts for most of array size
– Reduce cell size at expense of complexity
• 6T SRAM Cell
– Used in most commercial chips
– Data stored in cross-coupled inverters
• Read:
bit
word
– Precharge bit, bit_b
– Raise wordline
• Write:
– Drive data onto bit, bit_b
– Raise wordline
Size 26 x 45 λ
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bit_b
SRAM Read
• Precharge both bitlines high
• Then turn on wordline
• One of the two bitlines will be
pulled down by the cell
• Ex: A = 0, A_b = 1
– bit discharges, bit_b stays
high
– But A bumps up slightly
• Read stability
– A must not flip
N1 stronger than N2
(N1 has lower resistance)
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Reading within the context of a column
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SRAM Write
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Drive one bitline high, the other low
word
Then turn on wordline
Bitlines overpower cell with new value
Ex: A = 0, A_b = 1, bit = 1, bit_b = 0
– Force A_b low, then A rises high
• Writability
– Must overpower feedback inverter
bit_b
bit
P1 P2
N2
N4
A
A_b
N1 N3
A_b
A
1.5
bit_b
N4 stronger than P2
(N4 has lower resistance)
1.0
0.5
word
0.0
0
100
200
300
400
time (ps)
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500
600
700
SRAM Column Example
Bitline Conditioning
Bitline Conditioning
2
2
More
Cells
More
Cells
word_q1
word_q1
H
SRAM Cell
write_q1
out_b_v1r
1
2
word_q1
bit_v1f
out_v1r
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out_v1r
data_s1
bit_b_v1f
bit_v1f
H
bit_b_v1f
bit_v1f
SRAM Cell
2. Decoders
• n:2n decoder consists of 2n n-input AND gates
– One needed for each row of memory
– Build AND from NAND or NOR gates
A1
A0
Static CMOS
word0
word1
word2
word3
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Large decoders
• For n > 4, NAND gates become slow
– Break large gates into multiple smaller gates
A3
A2
A1
A0
word0
word1
word2
word3
word15
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Predecoding
• Many of these gates are redundant
– Factor out common
gates into predecoder
– Saves area
– Same path effort
A3
A2
A1
A0
predecoders
1 of 4 hot
predecoded lines
word0
word1
word2
word3
word15
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3. Column circuitry
• Some circuitry is required for each column
– Bitline conditioning
– Sense amplifiers
– Column multiplexing
wordlines
bitline conditioning
bitlines
row decoder
memory cells:
2n-k rows x
2m+k columns
n-k
column
circuitry
k
n
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column
decoder
2m bits
Bit preconditioning and sense amplifiers
• Precharge bitlines high before reads
bit
•Many words in memory
bit capacitance is huge
slow reading (large memory access time)
•Sense amplifiers are triggered on small voltage
swing (reduce DV)
sense_b
bit
P1
N1
P2
N2
N3
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sense
bit_b
bit_b
Column multiplexing
• Recall that array may be folded for good aspect ratio
• Ex: 2 kword x 16 folded into 256 rows x 128 columns
– Must select 16 output bits from the 128 columns
– Requires 16 8:1 column multiplexers
B0 B1
B2 B3
B4 B5
B6 B7
B0 B1
B2 B3
B4 B5
A0
A0
A1
A1
A2
A2
Y
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to sense amps and write circuits
Y
B6 B7