Transcript Overview - VLSI-EDA Laboratory

CMOS Digital Integrated Circuits
Lec 9
Super Buffer Design
1
CMOS Digital Integrated Circuits
Supper Buffer
Supper Buffer
Cload

Given a large capacitance load Cload
• How many stages are needed to minimize the delay?
• How to size the inverters?
Equiv INV
1
1
Cg
Cd
Cg
N
2
Cd
2Cg
2Cd
NCg
NCd
Cload
N: number of inverter stages
: optimal stage scale factor
2
CMOS Digital Integrated Circuits
Supper Buffer (Cont.)
where
•
•
•
•
•
3
Cg: the input capacitance of the first stage inverter.
Cd: the drain capacitance of the first stage inverter.
Each inverter is scaled up by a factor of  per stage.
Cload = N+1Cg
All inverters have identical delay of 0(Cd+Cg)/(Cd+Cg) which 0 is
per gate delay for Equiv INV in ring oscillator circuit with load
capacitance = Cg+Cd
CMOS Digital Integrated Circuits
Supper Buffer Design
Equiv INV
1
1
Cg
d
Cd
Cd
Cg
d
N
2
2Cd
2Cg
d
NCg
NCd
Cload
d
• Consider N stages, each inverter has same delay 0(Cd+Cg)/(Cd+Cg).
Therefore,
 C d  C g 




N

1
 total
 0 


C
C
d
g


4
CMOS Digital Integrated Circuits
Supper Buffer Design (Cont.)
• Goal: Choose  and N to minimize total.
» By Cload = N+1Cg, we have


ln  C load 
N  1   C g 
ln 
» Plug the above equation into total, we get
 C load 

ln 
C g   C d   C g 

 total 
0

ln 
 Cd  C g 
» To minimize total:
1






 total  ln  C load     C d   C g   1  C g   0
0 
2





 C g    ln    C d  C g  ln   C d  C g 


 opt ln  opt 1 
5
Cd
Cg
CMOS Digital Integrated Circuits
Supper Buffer Design (Con.)
» For the special case Cd=0  ln(opt)=0  opt = e. However, in
reality the drain parasitics cannot be ignored.
• Example: For Cd=0.5 fF, Cg=1 fF, determine opt and N for Cload = 50
pF.
opt (ln opt -1) = 0.5  opt = 3.18
N 1 
ln C load / C g 
ln  opt
N  ln C load / C g  / ln  opt  1
 ln 50  1012 / 1  1014  / ln 3.18  1
 6.36
The Super Buffer Design which minimizes total for Cload = 50 pF is
N=7 Equiv INV stages, and opt = 3.18
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CMOS Digital Integrated Circuits
CMOS Ring Oscillator Circuit
• Oscillation period T is equal to
T=PHL1+PLH1+PHL2+PLH2+PHL3+PLL3
=2p+2p+2p
=3·2p=6p
• For arbitrary odd number (n) of cascade-connected invertes, we
have
f=1/T=1/(2·n·p)
• Also, we can write
p=1/(2·n·f)
1
V1
Cload,1
7
2
V2
Cload,2
3
V3
Cload,3
CMOS Digital Integrated Circuits
Voltage Waveforms of Ring Oscillator
Vout
VOH
V2
V1
V3
V2
V1
V3
V50%
VOL
t
τPHL2 τPLH3 τPHL1 τPLH2 τPHL3 τPLH1
T
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CMOS Digital Integrated Circuits