Transcript A Low-Cost SOC Debug Platform Based on On

Presenter : Shoa-Chieh Hou
SOC Conference, 2009. SOCC 2009. IEEE
International
While the complexity of System-on-a-Chip (SoC) design
keeps growing rapidly, today the need for an efficient
approach to catch design errors at silicon stage has
become an urgent issue. In this paper we present a
platform for silicon debugging that makes use of an
existing test architecture and thus can provide many
powerful debug features while requiring very low extra
overhead. It supports multi-core debugging for general
purpose cores in an SOC chip with the capabilities of online tracing, hardware breakpoint insertion and cyclebased stepping. An automatic design tool is also
developed to cooperate with the debug platform.
Together users can easily control debug operations and
examine trace results to efficiently identify the root cause
of failures in the silicon.
My thesis
HW side
Multi-TAP
controller
DASTEP
SW side
Scan-base
wrapper
McMaster
university
Trace
technique
Coresight…etc
SW/HW Co-debug Platform[2012]
Low-Cost SoC Test Platform[2009]
…..
An Embedded Processor Based SOC Test Platform[2005]
GDB(SW debug)
This paper
Past
work
Run-Stop
debug
In-Circuit
Emulator[3,4]
Infrastructures for
platform
Signal Trace
[12]
Platform
base[9,10]
Infrastructure
IPs[5]
Multi-Core issue
ICE
HW[3]
ICE
SW[4]
For
Core[9]
SoC
base[10]
NoC Debug[6]

Increasing of the chip complexity



Gap between simulation and real circuits


Some problem happened in simulation, some in real IC
JTAG is widely used method




Bug also increase
Time to market
ICE
Run stop mechanism
Trace
Method for SoC full test

Virtual level simulation



On-line trace and comparison





Post-silicon debug(simulation)
Capture the simulation result as data A
In FPGA or real case test
Trace rough data from bus or IP I/O
Capture the result as data B
Compare data A and B, and make sure with IP had
problem
HW breakpoint insertion and single stepping


Use run-stop mechanism to capture more detail data as
data C
Compare data C and data A to find the error in SoC
Calculated
address and
allows TAM
controller to
access
memory
Send enable
signal to
core while
TAM like a
slave
For scan
wrapper
setup and
output
Break-Point
Setup
Controller
Generate
1149.1 control
signal for scan
Signal
Core_en
0
1
Scan_en
0
1
Breakpoint
1
1
Debug_hold
0
1
Test Platform
Integration
Debug
Library
Application
Program
Debug HW
Generation
Debug SW
Integration
Setup File
Test Platform(HW)
Test Program(SW)
Debug Program(HW)
Debug
Program(SW)
TAMC Setup File
Expected
Response
Extraction
Expected
Responses
Debug Pattern
Transformation
Transformed
patterns

The paper propose




Full system for SoC test and debug
Automation tool for environment build
Allow multi-core trace and run-stop debug
Low cost in total SoC area

Platform is like our debug environment



JTAG base
Multi JTAG port
TAM controller architecture can be use in our
environment


Modify for simple
Buffer, B.P., shift mechanism design can be reference
TMS
TCK_1
…
...
TCK
TCK_N
TRST_1
…
...
TRST
TRST_N
buffe
r
TDI(without
ID)
…
...
TDI(with ID)
TDI_1
TDI_N
ID
Decoder
ID
TDO_1
TD
O
…...
...
Encode
r
…...
...
TDO(with
ID)
TDO_N
TCK_1
TRST_1
TCK
TMS
Core TAP #1
TDI_1
TDO_1
TMS
TDI(with
ID)
…………………
……….
TRST
TAP
controller
TCK_N
TRST_N
TMS
TDO(with
ID)
TDI_N
TDO_N
Core TAP #N