Transcript PLD - SJTU

Embedded System
JTAG interface
Reference
• IEEE Standard Test Access Port
and Boundary-Scan Architecture
IEEE Std 1149.1-2001
• AN 39: JTAG Boundary-Scan Testing
in Altera Devices
Altera Co.
What is JTAG?
• JTAG
– Joint Test Action Group
• BST
– A standard Boundary-Scan
Testing interface
Why JTAG?
• A Uniform Test Interface
• Daisy Chain for Multiple IC
Test
• ISP
• Debugging
History of JTAG
• 1985
– Joint European Test Action
Group(JETAG) formed in Europe
• 1986
– The group expanded
• 1988
– JTAG Version 2.0
• 1993
– IEEE Std 1149.1a-1993
Boundary-scan Testing
BST Pins
TCK
TMS
TDI
TDO
TRST
IC
Description of BST Pins
Functional Model IEEE Std.
1149.1 Circuitry
TDI
TMS
TDO
Ctrl
Shift Phases
Shift mode,
internal
control signal
not changed
red: path of
internal signal
Blue: shift
signal path
Shift & Update Phases
replace
internal
control signal
with shifted
signal (blue)
Capture Phase
Capture
original
internal
control signal
SAMPLE/PRELOAD Mode vs.
EXTEST Mode
SAMPLE/PRELOAD Mode
EXTEST Mode
Capture internal signal
without affect chip operation
Capture internal signal and
control chip outputs
Registers of BST
• Boundary-scan Register
a shift register consists of all the
boundary-scan cells of the device.
• Bypass Register
a 1-bit-long data register used to
provide a minimum-length serial path
between TDI and TDO
• Instruction Register
determine the action to be performed
and the data register to be accessed
Pull-up Registers For
TAP Controller
TAP FSM
How to reach SHIFT_IR state?
From the RESET state,
TMS is clocked with the
pattern 01100 to
advance the TAP
controller to SHIFT_IR
BYPASS Instruction
Mode (1)
Connection Modes (1)
Connection Modes (2)
Dead Lock in JTAG
EN
IC
En
Rst
PLD
En
Rst
Power
Supply
IC
TDI
TDO
Using JTAG to Program FlashROM
(System Block Diagram)
Address
CPU
JTAG
Data
FlashROM
Access Printer Port
J-Flash
Give IO
WinXP
Printer Port