Transcript At the core of the user experience.® On Chip Instrumentation as a Verification Tool FMCAD - Pre and Post Silicon Verification in the Industry.

At the core of the user experience.®
On Chip Instrumentation
as a Verification Tool
FMCAD - Pre and Post Silicon Verification
in the Industry Workshop
Nov. 2006
First Silicon Solutions Division
of MIPS Technologies Inc.
Rick Leatherman [email protected]
Neal Stollon [email protected]
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At the core of the user experience.®

MIPS Technologies is Leader in High Performance
Embedded RISC Processors
TM
®
 MIPS32 34K Multi-threaded RISC Processor Core
 Full range of 32 and 64 bit processor IP based on
common MIPS ISA

FS2 is Instrumentation IP and Tools Division of MIPS
®
 On-Chip Instrumentation (OCI ) Leadership
 Integrated Trace and Analysis Solutions for
Embedded Processor, On- Chip Bus and Logic

Processor and Bus OCI and tools for SoC systems
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Eclipse Based Tools Support
Extended performance analysis advanced features
High performance Data trace port options
Tighter integration to EDA flows
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At the core of the user experience.®
The System Analysis Issue
• Methodology migrates from hardware to software bugs
• Need to comprehend the software needs at the hardware stages
• Customers and venders starting to realize
the job does not stop at the dotted line
Focus on Hardware Bugs
RTOS
Integration
System
Analysis
Focus
System
Initialization
RTL
Diagnostics
Instruction
Level/
Bus
Functional
Copyright © 2003 Novas Software, Inc.
Focus on Software Bugs
ESL
Application
Software
Multi-core
Integration
issues
Point were Hardware is
“assumed working”
Hardware
Hardware
Software Debugger
Simulation Prototype/Emulation System platform
Verification Abstraction
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At the core of the user experience.®
Highly Integrated Designs
Require System Level Debug Tools

Test based solutions (Scan, BIST) are not interactive, do not
provide cause and effect information
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Processor centric debugging (i.e. Instruction Trace) only solves
part of the problem
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Frequently chip bring-up problems are bus related
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Saturation, latch-up, etc.
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Performance optimization is interaction of cores, buses, IP
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Processor debug tools are of limited help
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On-chip Bus Analyzers and Multicore Embedded Debug Tools
Needed to Provide System Level Debug Features
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At the core of the user experience.®
Emerging SoC Debug and Analysis Issues

Debug and trace is crucial to embedded design success
 Difficult to fix what you can not see
 Unexpected on-chip Inter-relationships not always intuitive

System on Silicon Debug Requirements
 Visibility into non-observable sub-system interfaces
 On-chip debug analysis complements EDA verification
 Interoperability with processor debug capabilities
 Cross-triggering, synchronization for full view of problems
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Performance Analysis on buses, caches, execution cores, coprocessors, interrupts, peripherals, . .
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Debug IO requirements
 Leverage existing interfaces ie. JTAG
 Additional options to provide more analysis bandwidth
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At the core of the user experience.®
Multicore Debug Is Becoming Prevalent
Range of On-Chip Instrumentation IP and tools
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Customizable for specific customer requirements
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Multi-core cross triggering and synchronous control and
actions (go, halt and breaks)
Multi-core trace with wide ranges of features
measure activity on buses, caches, execution cores, coprocessors, interrupts, peripheral device events, . . .
Probes designed for trace and system debug
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Merging debug for several cores over single probe
Probe Hardware and tool API’s to support multi-core trace
Simple Control/data transfer via a single JTAG TAP
Support for multiple instantiations of source level debuggers
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At the core of the user experience.®
IP Complaint Solutions to SoC Analysis
IP
Centric
Products
SoC
Synergies
Instrumentation
Centric
Analysis
IP
Synergies
On Chip
IP
Processor
Cores
Enablement
Bus
IP
Prototyping
HW
Customer
Specific
IP
SW Dev.
tools
Bus
Level
Trace
Multi
Core
Debug
Probes
Infrastructure Synergies
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SoC
Performance
Analysis
System
Debug
tools
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At the core of the user experience.®
Plug and Play System Debug
Debug Support for Systems with Multiple Processors, Buses and Other IP Provides Complete Visibility Into Highly Integrated Designs
Typical solutions include:

Processor core + on chip bus analyzer
 Support for industry bus standards (AMBA, OCP)
 Custom solutions for proprietary buses
 Supports cross triggering between the bus analyzer and core
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Cores from different IP venders
 Support for proprietary cores frequently required
 Support synchronous go/halt/step & cross triggering between cores
 On-chip Logic Analyzers for “other” peripherals, accelerators, etc.
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Multiple cores + on chip bus analyzer
 Cross triggering, timestamping, synchronization
 System level event monitoring and debug control
 Trigger between cores and bus analyzer
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At the core of the user experience.®
MultiCore vs. Processor Debug
Multicore Debug addresses different issues for processor debug
Both are aspects of the same problem System Analysis and Optimization
 Communications vs. Computation
 Architecture Optimization vs. Algorithm Optimization
 Complementary- Both are required for full system view
 Equally important – priorities at different stages of debug.
Multicore
Debug
MANY
FACTORS
TO
CONSIDER
Processor
Debug
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At the core of the user experience.®
Platform Based System Design
Typical Features
 Diverse bus fabric options
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multiple processors
other blocks of IP
Differing clock domains
IO constrained
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(security, video,
imaging . . . )
OCP/AMBA
More than one core
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lots of data transfers
Differing bus interfaces
Other IP blocks
MIPS32®
34KTM
System Bus Fabric
OCP/AMBA
Other cores
Embedded operations of interest
not accessible by outside world
Problems show up in real time

Mem
Cntl
RAM
hard to emulate or reproduce
SO HOW CAN WE ADDRESS SoC VERIFICATION BETTER ?!?
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At the core of the user experience.®
MIPS Analyzer GUI
Integrated System Level Debug
System Debug Support for Multiple Processors,Buses
and Other IP - Visibility Into Highly Integrated Designs
 Single link (System Navigator probe) to target SoC for
system debug control, monitoring trace, cross triggers, …
 Access to all EJTAG and PDTrace debug facilities
 Bus Navigator, Logic Navigator, HyperDebug Instruments
JTAG Chain
System
Navigator
Probe
MIPS
EJTAG
PDTrace
24K/34KTMCore
Logic (IP)
Analyzer
(security,
HyperDebug
Cross Trigger
Debug Control
OCP
OCP / AHB
Custom
Bus Analyzer
Bus Navigator GUI
Other IP
video,
imaging . . . )
MIPS32TM
System Bus Fabric
Other MIPS
Other cores
EJTAG
Other FS2 Analyzers
Memory
Controller
HyperDebug
Cross trigger Chain
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At the core of the user experience.®
Starting Point is Processor Debug
MIPS EJTAG - is a leading example
 run control for each core - start, stop, breakpoint, single-step
 Hardware and software breakpoints
PDTrace adds processor trace capability
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Real time Instruction and data Trace - up to 64 bits per cycle
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Trigger on execution, RAM operations, address or opcode values
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Execution trace compression (Branch Trace Messages)
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Trace funneling for support of multiple MIPS core instances
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GDB and commercial Debugger support
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At the core of the user experience.®
Debug Software for Multi-Core Platforms
• Standards based debug IDE - Plug and play with 3rd party tools
• User transparent concurrent debug access (many cores/many debuggers)
• Standard based Eclipse, Tcl/TK, MDI, XML, text based scripting
MIPS Debugger
GUI
Tcl/TK
Command Line
Interface
Trace/Trigger
GUI
MDI
MIPS Debugger
GUI
MDI
EJTAG API
Nav. API
EJTAG API
Other
Debug GUI
MDI
Other API
Multicore ABI - Probe Drivers
USB, Ethernet
FS2 System
Navigator Probe
Off-Chip
TRACE PORT
OR
JTAG IO
On-Chip
34K
Other MIPS
EJTAG/
PDTrace
EJTAG/ PDTrace
Bus
Trace
OCI
Cross
Trigger
OCI
Other
OCI
Bus Fabric
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At the core of the user experience.®
On Chip Vs. Off Chip Instrumentation Solutions
On Chip (JTAG) trace
• Buffers signal trace on chip
• Requires on chip RAM
• Uses JTAG port for IO
•Simpler, cheaper Sys Nav probe
• All logic analyzer functions on chip
- several 10K gates on-chip
• Trace is function of on chip RAM
For more options with no extra debug
IO, On Chip approach is right choice.
Off Chip (Streaming) trace
• Streams data through parallel port
• Limitation is IO bandwidth
• Simpler OCI - Less logic on chip
• Logic analyzer is in probe
- Trace RAM & trigger logic is in probe
For very deep trace or reduced on-chip
debug gates, Off Chip is right choice.
OCI 1
Bus
Trace
RAM
OCI 2
Perf
Anal.
RAM
JTAG
JTAG
Probe
4 pins
OCI 3
PDTrace
OCI 1
Bus
Trace
OCI 2
Perf
Anal.
RAM
DEBUG
FUNNEL
1-64
pins
Streaming
Trace
Probe
OCI 3
PDTrace
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At the core of the user experience.®
Bus Navigator OCI IP Overview
PDTrace
----------EJTAG
Other IP blocks
MIPS32®
24KTM
(security, video,
BUS NAVIGATORTM OCI
Performance Time
stamp
counters
imaging . . . )
Trigger/trace
control
OCP/AMBA
System Backplane
JTAG IF
Trace Port
Trace
RAM
MIPS32®
34KTM
PDTrace
----------EJTAG
Mem
Cntl
Cross triggers
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Wide trace capability (256 signals)
to support for >1 bus channel
Programmable event monitoring
Configurable triggers, counters
Trace filtering and alignment
Trace limited by RAM size or Port Bandwidth
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At the core of the user experience.®
Bus Navigator Trace GUI
Complete Visibility into Your SOC Design
Waveform
Display
State
Display
Timestamps and Complex Event Triggers
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At the core of the user experience.®
Bus Navigator Integrated with Processor Debug
• Processor operations can drive system debug operations and vice versa
• Example: Cross-Triggering Bus Trace with MIPS Source Code
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At the core of the user experience.®
Case Study : Mobileye EyeQ2 Architecture
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Complex automotive image processor IC
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Debug Performance and bottlenecks
 Bus latency and throughput analysis
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10 cores (two MIPS 34K, DSPs, DMA)
Complex OCP/AMBA system network
Multi-layer Sonics SMX
Complex memory subsystems
Trace concurrent bus transactions
Trace full address for any transaction
Correlate Bus transactions to processor
Instructions, load/store operations
Track active threads to bus operations
Trace at least one image frame (>1 Gbyte)
Low overhead debug solution (minimal buffering)
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At the core of the user experience.®
Instrumentation Solutions for Mobileye (RRT)
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Request-Response Trace – Real time Bus Transaction Analysis
Solution built around FS2 System Navigator Pro Probe
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64 pin target interface
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Deep (2 Gbyte) Probe Trace Buffer
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Complex triggers, timestamps, . . .
Minimized on chip Logic
Complex trace resources in probe
Multicore PDtrace Funnel IP
PDtrace/RRT Correlation in SW
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Request-Response delay analysis
PDtrace/RRT Bus Correlation
Inferred thread to bus analysis
RRT Agent
(capture,
filter,
format)
Multicore Mictor 1
PDtrace
Funnel/
Port
JTAG
port
FS2
System
Navigator
Pro
Probe
RRT Agent
Upgraded PDtrace for multicore trace
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MIPS 1
(34K 2x
OCP)
Multi-frame trace
RRT agents and funnel IP
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MIPS 0
(34K 2x
OCP)
Allows processor and bus trace
VCE
(XB1
OCP)
DMA
(AHB)
RRT Trace Funnel
(combiner/
Scheduler)
RRT
Trace
Port
Mictor 2
RRT Agent
RRT Agent
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At the core of the user experience.®
System Level Performance Analysis
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Types of analysis that Navigator supports
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Measure activity - bus utilization, caches efficiency,
coprocessors activity, interrupts, peripheral device events
Measure latencies - interrupts, bus access, DMA transfers
Loop times of processing network packets, DSP Blocks
Monitoring bus bandwidth utilization, efficiency
Caches hit/miss ratios, DRAM pages, processor stalls
FS2 Navigator enables Analysis of System operations
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Free running timestamps allow interval measurements
relative to real time
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Counter and trigger resources allow real time event rates or
duration measures
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At the core of the user experience.®
So. What are open issues
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Standardization
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Most current solutions are proprietary.
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There are standardization efforts ongoing - next slide
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More end user and academic support will be needed
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Better Methods
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Biggest bottleneck is trace bandwidth and size
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New, better trace compression is needed for bigger SoC
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Design for Debug Awareness
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Too often, problems are not understood until post silicon
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More formal methodology for addressing instrumentation needs
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EDA integration
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Post silicon analysis and pre-silicon analysis are handled differently
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Open areas in addressing common tools and interoperability
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At the core of the user experience.®
Some Post Silicon Verification Related
Standards efforts
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Nexus Forum – IEEE 5001
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Nexus Addresses higher performance processor debug interfaces
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Affiliate membership is available to Academic groups
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OCP-IP Debug Working Group
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OCP is open bus protocol for complex SoC designs
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Debug group is working on standardized methods for SoC
Instrumentation
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SPIRIT Debug Working Group
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SPIRIT is vender neutral format for passing IP data to EDA tools
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Debug working group is working on standardized extensions for
Instrumentation and debug SW#
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MultiCore Association Debug Working Group
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Addressing API level interfaces for Multicore debug
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At the core of the user experience.®
FS2 Solutions for MIPS Systems
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FS2 offers sophisticated debug tools for SoC systems.
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System Navigator probe concurrently supports range of System OCI
options for SoC debug and analysis
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Trace Support for all MIPS cores
 True Plug-and-Play integration with leading MIPS Debuggers
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Bus (OCP/AMBA/Custom) Navigator debug/trace solutions
 Customizable for specific customer requirements
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Supported by FS2 Cross triggering, and analysis software
www.fs2.com gives you the details
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System Navigator Pro (deep trace) probe expends options
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Allows smaller on-chip component (more debug pins)
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System On Chip Instrumentation for is available now
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At the core of the user experience.®
FS2 Comprehensive
Debug Solutions
Software Tools and Interfaces
• Integrated with GDB/Insight
• New Eclipse IDE
• Supports 3rd party debuggers via MDI
• RTOS awareness
Embedded Instrumentation IP
• EJTAG, PDTrace, iFLowtrace
• Complex Triggers
• Integrated Bus Analyzers
• Multi-Core debug
• Performance Analysis
• Application specific debug blocks
System Navigator Probes
• USB 2.0 and Ethernet host
PC connections
• 14-pin (EJTAG & on-chip PDTrace)
or 38-pin Mictor (EJTAG & off-chip
• PDTrace) target connections
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At the core of the user experience.®
Eclipse Gaining Wide Acceptance

Eclipse IDE and CDT Debugger
 Eclipse is an modern IDE gaining wide acceptance in
the EDA and tools marketplace
 CDT (or C/C++ Debug Tools) is the native Eclipse
debugger for C/C++ code
 Eclipse “Plug-Ins” are built on well defined API’s
allowing third parties to enhance the debug
experience with their specific tools
 Create “views” for application specific solutions
Eclipse is an integrated development environment (IDE) that
combines a code editor, compiler, debugger, text editor, graphical user
interface (GUI) builder, and other components into a single, user-friendly application
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At the core of the user experience.®
View all thread
information after hitting
breakpoint, including
name, running state,
priority, etc
If thread suspended,
shows responsible
kernel component(s)
causing suspension
“cpu context” view
added to denote
execution in nonthread or ISR context
View of ThreadX
objects – TIMER,
QUEUE,
SEMAPHORE,
MUTEX,
BYTE_POOL
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