Transcript Document

13. System Architecture
Dezső Sima
Fall 2006
 D. Sima, 2006
Overview
• 1 Introduction to system architectures
•
2 The evolution of the system architecture
•
3 The evolution of Intel’s x86 processor bus
•
4 Bus innovations introduced in intel’s P4 chipsets
•
5 Chipsets of Intel’s P4 family
•
6 Bandwidth considerations
•
7 Special aspects of the implementation
1. Introduction
Concrete architecture
P entium P ro
P rocessor
Abstract architecture
Pentium Pro
system
Host bus
Application programming
OS
Graphics
adapter
82443LX
P CI/A.G.P .
Controller
(P AC)
A.G.P . Bus
Display
72 Bit
w/ECO
Main Memory
3.3V EDO &
SDRAM Support
application program interface
P CI Slots
P rimary P CI Bus
(P CI Bus #0)
System level
operating
system
2 IDE P orts
(Ultra DMA/33)
I/O controller
Logical I/O interface
User interface
2 USB P orts
System Mgnt (SM) Bus
82371SB
(P IIX4)
(P CI-to-ISA
Bridge)
USB
USB
ISA Slots
ISA Bus
System BIOS
Data carrier interface
Icache
data carrier
Pentium Pro
128
I-buf f er
Fetch
Decode, convert
to uops
D1
D2
D3
MIS
1 uop/cycle
4 uops/cycle
Issue
Reg. Mapping Table
Map reg. numbers
Reg. numbers
3 uops/cycle
ISA
Fetch operands
3 uops/cycle
RRF
32
Processor level
ROB
32
Operands
Pentium Pro
Processor
Shelve
RS
Port 0
20
Dispatch
Port 1
Port 2
Ports 3, 4
AU
AU
FMUL
FDIV
FADD
Execute
JEU
ISHF
IU
IDIV
IU
Feedback results
f or updating
Store Addr.
Store Data
Load Addr.
Memory Reorder B uf f er
Store
AU
D1 - D2
D3
MIS
IU
JEU
FMUL
Halbst age 0
:
:
:
:
:
:
Address G eneration Unit
Decoders
G eneralised decoder
Microinstruction Sequencer
Integer Unit
Jump Execution Unit
(branch target address generation)
Load
IDIV
ISHF
FADD
FDIV
FMUL
:
:
:
:
:
Integer Divide Unit
Integer Shif t Unit
FP-Adder
FP-Divider
FP-Multiplier
Op A
Op B
Input lat ch
Input lat ch
Boot h encoder
FMUL
P art ial
product
generat ion
Halbst age 1
Functional unit level
PC
PS
P art ial
product
generat ion
Halbst age 2
PC
PS
Add
Halbst age 3
Round
Figure 1.1.: Interpretation of the notion architecture at different levels
Renormalise
FP -regist er file
P C: P roduct Sum
P S: P roduct Carry
2. The evolution of the system architecture
2.1 System architecture of Intel’s desktop PCs - Overview
System architecture of Intel’s desktop PCs
ISA-based
8088/80286/
80386based PCs
Port-based
PCI-based
Simple
w/ATA,
USB
w/AGP,
ATA,USB
Early
implem.
486 and early
Pentium
based PCs
Mature
Pentium
based PCs
Early PII
and PIII
based PCs
Mature
PIII/P4
based PCs
P4 Prescott
based PCs
Intel 420
chipsets
Mature
Intel 430
chipsets
Intel 440XX
chipsets
Intel 8XX
chipsets
Intel 915X
chipsets
Evolution
Recent
implem.
2.2 Main steps of the evolution (1)
8088/80286/80386
Processor
Memory/
Bus controller
KBD
Main Memory
(DRAM/FPM)
ISA
Monitor
Adapter
WD
Adapter
FD
Adapter
PP
Adapter
SP
Adapter
Multi-I/O card
I/O devices
Figure 2.1: ISA-bus based system architecture
(Used typically in 8088/80286/80386-based PCs)
2.2 Main steps of the evolution (2)
486/Pentium
Processor bus
L2 cache
System
controller
Main Memory
(FPM/EDO)
PCI bus
Peripheral
controller
PCI device
adapter
ISA bus
ISA device
adapter
(Legacy and/or
slow devices)
Figure 2.2: Simple PCI-based system architecture
(Used typically in 486 and early Pentium-based PCs along with Intel 420 and early 430 chipsets)
2.2 Main steps of the evolution (3)
Pentium
Processor bus
L2 cache
System
controller
Main Memory
(FPM/EDO/SDRAM)
PCI bus
IDE/(ATA/33)
IDE port: First on the 430FX (Triton, 1995)
USB
Peripheral
controller
ATA/33: First on the 430TX (1997)
PCI device
adapter
USB:
First on the 430VX (Triton III, 1996)
ISA bus
ISA device
adapter
(Legacy and/or
slow devices)
Figure 2.3: PCI-based system architecture with IDE/ATA and USB ports
(Used typically in mature Pentium-based PCs with mature Intel 430 chipsets)
2.2 Main steps of the evolution (4)
PentiumII/
PentiumIII
PentiumII/
PentiumIII
Processor bus
AGP
System
controller
Main Memory
(EDO/SDRAM)
PCI bus
2xIDE/ATA33/66
Peripheral
controller
PCI device
adapter
(Legacy and/or
slow devices)
2xUSB
ISA bus
ISA device
adapter
Figure 2.4: PCI-based system architecture with AGP, IDE/ATA and USB ports
(Used typically in PentiumII and early PentiumIII-based PCs with Intel 440XX chipsets)
2.2 Main steps of the evolution (5)
PentiumIII/
Pentiu4
Processor bus
AGP
System
controller
Main Memory
(SDRAM/)
Hub interface
LPC
2xIDE/
ATA 33/66/100
Peripheral
controller
Super I/O (KBD, MS, FD, SP, PP, IR)
AC'97
2x/4x USB
(Used typically in PentiumIII and
Pentium4-based systems with Intel
8X0 chipsets)
PCI bus
PCI to ISA
bridge
PCI device
adapter
ISA bus
ISA device
adapter
(Legacy and/or
slow devices)
Figure 2.5: Early port-based system architecture
2.2 Main steps of the evolution (6)
Pentium 4
Processor bus
PCI E.x16
System
controller
Main Memory
(SDRAM/)
Hub interface
1xIDE/
ATA 33/66/100
8x USB
PCI E.x1 (1x/2x)
Peripheral
controller
LAN 10/100
LPC (KBD, MS, FD, SP, PP, IR)
AC'97
4x SATA
HDAI
PCI bus
PCI device
adapter
Figure 2.6: Recent port-based system architecture
3. The evolution of Intel’s x86 processor bus
Main features of the system-bus
Width of the
address bus (bit)
data bus (bit)
1
2
3
4
8086
1
20
16
1
8088
20
8
1
1
80286
24
16
80386
32
32
2
80486
32
32
2
Pentium Pro
PII,PIII
Pentium
32 3
64
Multiplexed
Bits 0,1 not implemented (Doubleword aligned)
Bits 0-2 not implemented (Quadword aligned)
For error protection
Figure 3.1: Main features of the system-bus
36
36
64+8
P4
4
64+8 4
4. Bus innovations introduced into Intel’s P4 chipsets (1)
11/02
AGP 8x
AGP
5/03
SATA 1.0a
SATA
5/03
PCI 2.3
PCI
2/04
PCI-X 2.2
PCI-X
6/04
PCI Express
PCI Express 1.0a
5/02
USB
USB 2.0
12/01
AC' 97
AC' 97 2.3
6/04
HDAI
HDAI
2001
2002
2003
Figure 4.1: Bus innovations introduced into Intel’s P4 chipsets
2004
4. Bus innovations introduced into Intel’s P4 chipsets (2)
The principle of the AGP port
Processor bus
AGP
Graphic chip
Memory bridge
(North bridge)
Frame buffer
I/O bridge
(South bridge)
Main memory
AGP
(Intel)
Main Features of the AGP port
Version 1.0
(7/1998)
(Based on Revision 2.1
of the PCI)
(PCI)
Clock speed
Bus
Transfer mode
Transfer rate
Version 2.0
(5/1998)
66 MHz
(Multiplexed 32-bit address bus
/data bus)
(Transfer of 4-byte data blocks)
Seperate 32-bit address bus
and 32-bit data bus
Transfer of 8-byte data blocks
1x
2x
4x
(AGP-66)
(AGP-133)
(double
clocked)
(AGP-266)
(quadruple
clocked)
264 MB/s
532 MB/s
1064 MB/s
Figure 4.2.: Early evolution of the AGP port
4. Bus innovations introduced into Intel’s P4 chipsets (3)
ISA
EISA
8.33 MHz
8/16-bit
8.33 MHz
32-bit
1987
88
89
PCI
PCI v.2
PCI v.2.11
PCI v.2.21, 3
PCI v.2.32
33/66 MHz
32/64-bit
33/66 MHz
32/64-bit
33/66 MHz
32/64-bit
33 MHz 33 MHz
32-bit
64-bit
90
91
92
93
94
1995
96
97
98
99
2000
1:
Both 3.3 V and 5 V is supported
Only 3.3 V is supported
3: Just improving the readibility of the standard text
2:
Figure 4.3: The evolution of the PCI bus standard
01
02
03
4. Bus innovations introduced into Intel’s P4 chipsets (3)
ISA
EISA
8.33 MHz
8/16-bit
8.33 MHz
32-bit
1987
88
89
PCI
PCI v.2
91
92
93
PCI-X v.2.02
66/133 MHz
64-bit
266/533 MHz
64-bit
PCI v.2.11
PCI v.2.21, 3
PCI v.2.32
33/66 MHz
32/64-bit
33/66 MHz
32/64-bit
33/66 MHz
32/64-bit
33 MHz 33 MHz
32-bit
64-bit
90
PCI-X v.1.02
94
1995
96
97
98
99
2000
1:
Both 3.3 V and 5 V is supported
Only 3.3 V is supported
3: Just improving the readibility of the standard text
2:
Figure 4.4: The introduction of the PCI-X
01
02
03
4. Bus innovations introduced into Intel’s P4 chipsets (5)
Figure 4.5: Slot number limitations of the PCI-X bus
Source: PCI Technology overview, Febr. 2003, http://www.digi.com/pdf/prd_msc_pcitech.pdf
4. Bus innovations introduced into Intel’s P4 chipsets (6)
The PCI Express bus (3GIO)
• PCI Express 1.0 introduced in 7/2002
• A link consists of 1x, 2x, 4x, 8x, 12x, 16x or 32x signal pairs (lanes) in each direction.
• Transfer rate per lane per direction: 2.5 Gbits/s
• Encoding 10 bits/byte
Aggreagate bandwidth per lane (in both directions together):
2 x 2,5 /10 = 0,5 Gbyte/s
4. Bus innovations introduced into Intel’s P4 chipsets (7)
ATA (PATA) cable
ATA/PATA and SATA cables
Figure 4.6.: Contrasting ATA/PATA and SATA cables
4. Bus innovations introduced into Intel’s P4 chipsets (8)
AC '97
Version 1.0
6/1996: 5 vendors
(Intel, ADI, Creative Labs,
National Semiconductor,
Yamaha).
Version 2.0
Revision 2.1
Revision 2.2
(9/1997)
(5/1998)
(9/2000)
Link:5-wire digital
(2 serial data lines)
Audio Codec
16-bit optionally
18/20-bit AD/DA
resolution
48 KHz sampling rate
4 analog stereo inputs
2 analog mono inputs
4/6 channel output
dedicated mic input
Digital controller
High Quality audio
(up to 96 KHz sampling rate
120 dB dynamic range)
Modem extension
(Cost effective)
Multiple codec
capability
(for multichannel
audio solutions etc.)
May reside on any bus
(ISA, PCI, USB, 1394) or
in an I/O-bridge
Figure 4.7.: Early evolution of the AC ’97 bus
4. Bus innovations introduced into Intel’s P4 chipsets (9)
High definition audio (HDA)
AC’97 v.2.2
No. of channels
6
HDAI
8
Resolution
20-bit
32-bit
Sampling rate
96 kHz
192 kHz
4. Bus innovations introduced into Intel’s P4 chipsets (10)
Pe ak ban dwidth
MByte /s
AGP 4X
1066
AGP 8X
2132
VGA port
S u stain e d data rate u p to
MByte /s
analog port
MbE c.
12.5
GbE c.
125
S C S I Ul tra 320
320
Ul tra ATA/100
100
~30-60/drive
S ATA 1.0
150
~30-60/drive
PC I 32-bit/33 MHz
133
PC I-X 64-bi t/66 MHz
533
PC I-X 64-bi t/133 MHz
1066
PC I E. x1
500
PC I E. x4
2000
PC I E. x8
4000
PC I E. x16
8000
US B 1.0
~125
60-90/drive, ~200-250/bus
~400-450
1.5
US B 2.0
60
AC '97
~1.4
HDA
3/SDI, 6/SDO
LPC
~5
~50
Figure 4.8: Peak bandwidth values and sustained data rates of peripheral buses
5. Chipsets of Intel’s P4 family
5.1 Overview of the P4 family
5.2 Desktop chipsets
5.3 Overview of DP server and workstation chipsets
5.4 DP server chipsets
5.5 DP workstation chipsets
5.1 Overview of the P4 family
Xeon - MP line
3/02
11/02
^
^
Foster-MP
Gallatin
0.18 m /108 mtrs
1.4/1.5/1.6 GHz
0.13 m/178 mtrs
1.5/1.9/2 GHz
On-die 256K L2
On-die 512K/1M L3
400 MHz FSB
On-die 512K L2
On-die 1M/2M L3
400 MHz FSB
mPGA 603
mPGA 603
Xeon DP line
2Q/05
3/04
^
^
Potomac
Gallatin
0.09 m
> 3.5 MHz
0.13 m/286 mtrs
2.2/2.7/3.0 GHz
On-die 1M L2
On-die 8M L3 (?)
On-die 512K L2
On-die 2M/4M L3
400 MHz FSB
mPGA 603
5/01
2/02
11/02
7/03
6/04
^
^
^
^
^
2Q/05
^
Foster
Prestonia-A
Prestonia-B
Prestonia-C
Nocona
Jayhawk
0.18 m/42 mtrs
1.4/1.5/1.7 GHz
0.13 m/55 mtrs
1.8/2/2.2 GHz
0.09 m
3.8 GHz
On-die 512K L2
400 MHz FSB
mPGA 603
0.13 m
/178 mtrs
3.06 GHz
On-die 512K L2, 1M L3
533 MHz FSB
mPGA 603
0.09 m/ 125 mtrs
2.8/3.0/3.2/3.4/3.6 GHz
On-die 256 K L2
400 MHz FSB
mPGA 603
0.13 m/55 mtrs
2/2.4/2.6/2.8 GHz
On-die 512K L2
533 MHz FSB
mPGA 603
On-die 1M L2
800 MHz FSB
mPGA 604
On-die 1M L2
(Cancelled 5/04)
11/03
11/04
1Q/05
^
^
^
Irwindale-B 1
Irwindale-A 1
Extreme Edition
0.13 m/178 mtrs
3.2EE GHz
On-die 512K L2, 2M L3
800 MHz FSB
mPGA 478
Desktop-line
Irwindale-C
11/00
8/01
1/02
5/02
11/02
5/03
2/04
6/04
8/04
^
^
^
^
^
^
^
^
^
Northwood-C 5
Prescott 8,9,10
Willamette
Northwood-A2,3
Northwood-B 4
Northwood-B
0.18 m/42 mtrs
0.18 m/42 mtrs
0.13 m/55 mtrs
0.13 m/55 mtrs
1.4/1.5 GHz
On-die 256K L2
400 MHz FSB
1.4 ... 2.0 GHz
On-die 256K L2
400 MHz FSB
2A/2.2 GHz
2.26/2.40B/2.53 GHz
On-die 512K L2
On-die 512K L2
400 MHz FSB
533 MHz FSB
mPGA 478
mPGA 478
0.13 m/55 mtrs
0.09 m/125mtrs
2.40C/2.60C/2.80C GHz 2.80E/3E/3.20E/3.40E GHz
3.06 GHz
On-die 512K L2
On-die 1M L2
On-die 512K L2
800 MHz FSB
800 MHz FSB
533 MHz FSB
mPGA 478
mPGA 478
mPGA 478
Willamette
mPGA 423
mPGA 478
5/02
^
Celeron-line
(Value PC-s)
Willamette-128
0.18 m
1.7 GHz
On-die 128K L2
400 MHz FSB
mPGA 478
2001
2000
Cores supporting hyperthreading
0.13 m/55 mtrs
0.09 m/125mtrs
2.8/3.0/3.2/3.4/3.6 GHz
On-die 1M L2
800 MHz FSB
LGA 775
9/02
6/04
9/04
^
^
^
Celeron-D 12
Northwood-128
0.13 m
2 GHz
On-die 128K L2
400 MHz FSB
2003
Cores with EM64T implemented but not enabled
3Q/05
^
Prescott-F 11
Tejas
0.09 m/
0.09 m/125mtrs
4.0/4.2 GHz
3.20F/3.40F/3.60F GHz
On-die 1M L2
On-die 1M L2
(Cancelled 5/04)
800 MHz FSB
LGA 775
Celeron-D 13
0.09 m
2.4/2.53/2.66/2.8 GHz
On-die 256K L2
533 MHz FSB
mPGA 478
mPGA 478
2002
Prescott 6,7
0.09 m
3.0/3.2/3.4/3.6 GHz
On-die 512K L2, 2M L3
0.13 m/178mtrs
3.4EE GHz
On-die 512K L2, 2 MB L3
1066 MHz FSB
LGA 775
0.09 m
2.53/2.66/2.80/2.93 GHz
On-die 256K L2
533 MHz FSB
LGA 775
2005
2004
Cores supporting EM64T
Figure 5.1: Intel’s P4 cores (Netburst architecture)
5.2 Desktop chipsets (1)
Cores
11/00
Willamette
400 MHz
5/03
Northwood-B
400 MHz
533 MHz
HT
8/04
Prescott
5/02
Willamette
400 MHz
2/04
Northwood-B
Northwood-A
8/01
FSB
11/02
1/02
Northwood-C
533 MHz
Prescott
800 MHz
800 MHz
HT
HT
HT
Prescott F
6/04
800 MHz
800 MHz
HT
HT
EM64T
Socket
EM64T
m PGA 423
m PGA 478
m PGA 478
m PGA 478
m PGA 478
m PGA 478
m PGA 478
LGA 775
LGA 775
8/03
Chipsets
848P
10/02
845GV/GE/PE
5/03
9/03
5/03
865G/GV/PE
5/03
9/01
845
5/02
11/01
845
845 G/E/GL
865P
4/03
875P
6/04
9/03
6/04
915G/GV/P
Figure 5.2: Intel’s chipsets designed for P4-based value and desktop PCs
5.2 Desktop chipsets (2)
9/01
845
5/02
8/03
845xx family
848P
(Brookdale)
5/03
4/03
865xx/875P family
(Springdale/Canterwood)
06/04
11/05
915xx family
975x
(Grantsdale)
MCH/GMCH
HT support
no HT
no HT/HT
HT
HT
HT
HT
FSB up to
400 MT/s
533 MT/s
800 MT/s
800 MT/s
800 MT/s
1066 MT/s
Nr. of mem. channels
Memory
Max. memory
DRAM speed up to
Dual channel
Dual channel
Dual channel
DDR SDRAM
(unbuffered)
DDR SDRAM
(unbuffered)
DDR2 /DDR SDRAM
(unbuffered)
DDR2 SDRAM
(unbuffered)
2 GB
2 GB
4 GB
4 GB
8 GB
DDR 333
DDR 400
DDR 400
DDR 400/DDR2 533
DDR2 667
CSA
CSA
AGP 8X
Single channel
Single channel
SDR/DDR SDRAM
(unbuffered)
SDR/DDR SDRAM
(unbuffered)
2 GB
DDR 266
Additional high speed
interface1
Graphics interface up to
ICH
ATA up to
Single channel
AGP 4X
AGP 4X
AGP 8X
ICH2:
ICH4:
ICH5/ICH5R:
Ultra ATA/100
Ultra ATA/100
Ultra ATA/100
SATA
PCI Express x16
PCI Express x16
ICH5/ICH5R:
ICH6/ICH6R:
ICH7/ICH7R:
Ultra ATA/100
Ultra ATA/100
Ultra ATA/100
SATA 1.0a
SATA 1.0a
10/100 Mbit/s
LAN
10/100 Mbit/s
10/100 Mbit/s
10/100 Mbit/s
PCI
PCI 2.2
PCI 2.2
PCI 2.3
PCI 2.3
AC' 97
AC' 97 2.1
USB 2.0
AC' 97 2.3
USB 2.0
3
PCI 2.3
PCI 2.3
AC' 97 2.3
2
PCI Express x1 1.0a
USB 2.0
USB 2.0
AC' 97 2.3
AC' 97 2.3
AC' 97 2.3
HDAI
HDAI
HDAI
2
10/100 Mbit/s
USB 2.0
3
1
10/100 Mbit/s
PCI Express x1 1.0a
USB 1.1
3
SATA 1.0a
2
PCI Express x1
USB
SATA 1.0a
The Communications Streaming Architecture (CSA) interface of the MCH provides a link to a Gigabit Ethernet Controller (GbE),
e.g. to Intel's 82547EI GbE controller
A GbE controller can be attached via the PCI Express x1 link providing 10/100/1000 Mbit/s speeds. (e.g. Intel's 82571EB
dual channel GbE controller)
The Intel High Definition Audio Interface (HDAI) shares pins with the AC '97 link, so these interfaces cannot be
operated concurrently
Figure 5.3: The evolution of Intel’s chipset families designed for P4-based value/mainstream desktops
5.2 Desktop chipsets (4)
P4
FSB
VGA
AGP 4X/8X/PCI Express x.16
1
MCH
SDRAM
interface
2
(845/845xx/848P/865xx/
875P/915xx)
SDRAM 3
interface
Max. 2/4 GB 4
PC 133, DDR 200/266/333/400, DDR2 400/533
SDRAM
unbuffered, ECC opt.
3
SDRAM
HI 1.5/DMI
ICH2
ICH4
ICH5(R)
6x v2.2
6x v2.2
6x v2.3
5
ICH6(R) 6
7x v2.3
ICH2
ICH5(R) 5 ICH6(R) 6
PCI
ATA/100
PCI-X
4
ICH4
PCI Express x1
ICH
2
2
2
2
SATA
1
5
46
LAN 10/100
4x v1.1
6x v2.0
8x v2.0
8x v2.0
v2.1
v2.3
v2.3
v2.3
USB
GPI0
AC/97
HDAI
845
1
2
845xx
848P
865xx
875P
915xx
LPC
ICH2/4/5/5R 5/6/6R 6
845
FWH
845xx
848P
865xx
875P
915xx
BIOS
The chipsets including the letter G in their designation provide an integrated graphics controller.
The chipsets including the letters GL or GV in their designation don't have an AGP or PCI Express x16 interface.
3
The 865xx, 865 and 915xx chipsets have a dual channel memory link..
The 845 has a max. memory of 3 GB for SDR SDRAMs.
5 The ICH5R includes an integrated RAID controller that utilizes the dual SATA ports for a high performance RAID Level 0 implementation.
4
6
The ICH6R includes an integrated RAID controller that utilizes the dual SATA ports for a high performance RAID Level 0 implementation.
Figure 5.4: The evolution of chipsets intended primarily for P4-based value/mainstream desktops
5.2 Desktop chipsets (3)
Part. nr.
ICH2
ICH3S
ICH4
ICH5/ICH5R
82801 BA
82801 CA
82801 DB
82801 EB/82801 ER
6300ESB
ICH6/ICH6R
ICH7/ICH7R
82801 FB/82801 FR
82801 FB/82801 FR
6/04
4/05
Initial release
6/00
2/02
5/02
4/03
2/04
Interface to the MCH
HI 1.5
HI 1.5
HI 1.5
HI 1.5
HI 1.5
2x Ultra AT A/100
2x Ultra AT A/100
2x Ultra AT A/100
2x Ultra AT A/100
2x Ultra AT A/100
1x Ultra AT A/100
1x Ultra AT A/100
2x SAT A
2x SAT A
4x SAT A
4x SAT A
6x v. 2.3
4x v. 2.2
7x v. 2.3
6x v. 2.3
4x v. 1.0a
4/6x v. 1.0a
8x v. 2.0
8x v. 2.0
AT A ports
1
2
SAT A ports
PCI masters
6x v. 2.2
6x v. 2.2
6x v. 2.2
PCI-X masters
LAN
AC' 97
DMI
4x v. 2.2
PCI Express x1 ports
USB ports
DMI
4x v. 1.1
6x v. 1.1
6x v. 2.0
8x v. 2.0
10/100 Mb/s
10/100 Mb/s
10/100 Mb/s
10/100 Mb/s
v. 2.1
v. 2.2
v. 2.3
v. 2.3
4x v. 2.0
v. 2.2
10/100 Mb/s
10/100 Mb/s
v. 2.3
v. 2.3
HDAI
GPIO
LPC
1
Each AT A port is capable to serve two AT A devices (a primary and a secondary device).
2
Each SAT A port is capable to serve a single SAT A device.
Figure 5.5: Main features of Intel’s I/O Control Hubs (ICH) used in P4-based chipsets
5.2 Desktop chipsets (1)
Cores
11/00
Willamette
400 MHz
5/03
Northwood-B
400 MHz
533 MHz
HT
8/04
Prescott
5/02
Willamette
400 MHz
2/04
Northwood-B
Northwood-A
8/01
FSB
11/02
1/02
Northwood-C
533 MHz
Prescott
800 MHz
800 MHz
HT
HT
HT
Prescott F
6/04
800 MHz
800 MHz
HT
HT
EM64T
Socket
EM64T
m PGA 423
m PGA 478
m PGA 478
m PGA 478
m PGA 478
m PGA 478
m PGA 478
LGA 775
LGA 775
8/03
Chipsets
848P
10/02
845GV/GE/PE
9/01
9/03
5/03
865G/GV/PE
5/03
845
11/01
845
5/03
5/02
845 G/E/GL
865P
4/03
875P
6/04
9/03
6/04
915G/GV/P
Figure 5.6: Intel’s chipsets designed for P4-based value and desktop PCs
5.2 Desktop chipsets (5)
Features
845xx family
MCH/GMCH
Memory
(Brookdale)
Single channel SDR/DDR SDRAM
(unbuffered)
1
2 GB
Max. memory
FSB
HT support
DRAM speed
PC133
9/01
Memory protection
11/01
400 MHz
533/400 MHz
HT not supported
HT supported
PC133,
DDR 266/200
12/01
845
845
ECC (opt.)
ECC (opt.)
Integrated graphics (IG)
Graphics interface up to
ICH
2
PC133,
DDR 266/200
PC133,
DDR 266/200
5/02
5/02
5/02
845G
845E
845GL
AGP 4X
ICH2:
ICH2:
IG
ICH4:
ICH4:
ICH4:
Ultra ATA/100
PCI 2.2
10/100 Mbit/s
LAN
Target line at introduction
Target core at introduction
2
DDR 333/266
DDR 333/266
10/02
10/02
845GE
845PE
IG
AGP 4X
AGP 8X
ICH4:
ICH4:
ICH4:
USB 1.1
USB 1.1
USB 2.0
USB 2.0
USB 2.0
USB 2.0
USB 2.0
USB 2.0
AC '97 2.1
AC '97 2.1
AC '97 2.3
AC '97 2.3
AC '97 2.3
AC '97 2.3
AC '97 2.3
AC '97 2.3
P4
P4
P4
P4
Celeron/P4
P4
P4
Willamette
0.18m
m PGA 478
1
845GV
AGP 4X
PCI
AC '97
10/02
IG
AGP 4X
ATA up to
USB
DDR 266/200
ECC (opt.)
IG
AGP 4X
DDR 266/200
Northwood-A
Celeron/P4
Willamette-128/
Northwood-A
0.13m
0.18m
m PGA 478
m PGA 478
Northwood-B
with HT
Northwood-128/
Northwood-B with HT
Northwood-B
with HT
0.13m
m PGA 478
The 845 has a max. memory of 2 GB for DDR SDRAMs and 3 GB for SDR SDRAMs.
At introduction of the 845G and 845E chipsets (5/02) Intel did not made any notice about supporting hyperthreading. But in 10/02 Intel revealed that the enhanced 845G (B stepping) and the original
845E do support hyperthreading with upgraded BIOSs.
Figure 5.7: Main features of Intel’s 845xx family of chipsets
5.2 Desktop chipsets (6)
P4
Northwood
FSB 400/533 MHz
1
VGA
AGP 4x
845xx 1,2
SDRAM
interface
(G)MCH
3
SDRAM
Max. 2 GB
DDR 200/266/333
unbuffered, no ECC
HI 1.5
MbE
MbE c.
GbE
GbE c.
LAN 10/100
PCI v.2.2
Ultra ATA/100
(2 ports)
ICH4
PCI v.2.2
(3-6 slots)
GPIO
USB 2.0
(4-6 ports)
Audio
CODEC
AC'97 v.2.3
LPC
FWH
SIO
FD
1
2
3
KB
MS
SP
PP
The chipsets including the letter G in their designation provide an integrated VGA controller.
Mainboards based on the 845 chipset have a different configuration since they work with the ICH2.
The chipsets 845GL/GV don't offer an AGP interface.
Figure 5.8: Typical configuration of a value/desktop motherboard based on Intel’s 845xx family of chipsets
5.2 Desktop chipsets (1)
Cores
11/00
Willamette
400 MHz
5/03
Northwood-B
400 MHz
533 MHz
HT
8/04
Prescott
5/02
Willamette
400 MHz
2/04
Northwood-B
Northwood-A
8/01
FSB
11/02
1/02
Northwood-C
533 MHz
Prescott
800 MHz
800 MHz
HT
HT
HT
Prescott F
6/04
800 MHz
800 MHz
HT
HT
EM64T
Socket
EM64T
m PGA 423
m PGA 478
m PGA 478
m PGA 478
m PGA 478
m PGA 478
m PGA 478
LGA 775
LGA 775
8/03
Chipsets
848P
10/02
845GV/GE/PE
5/03
9/03
5/03
865G/GV/PE
5/03
9/01
845
5/02
11/01
845
845 G/E/GL
865P
4/03
875P
6/04
9/03
6/04
915G/GV/P
Figure 5.9: Intel’s chipsets designed for P4-based value and desktop PCs
5.2 Desktop chipsets (7)
Features
915xx family
(Grantsdale)
HT supported
Dual channel DDR2/DDR SDRAM
(unbuffered, no ECC)
4 GB1
MCH/GMCH
HT support
Memory
Max. memory
FSB
DRAM speed
533 MHz
DDR 400/333
9/04
910GL4
(Grantsdale-GL)
Integrated graphics (IG)
IG
Graphics interface up to
1
2
3
4
915G
(Grantsdale-G)
IG
9/04
6/04
915GV
(Grantsdale-V)
915P
(Grantsdale-P)
IG
PCI Express x16
ICH6:
Ultra ATA/100
SATA 1.0a
PCI Express x1 1.0a 2
PCI 2.3
10/100 Mbit/s
AC '97 2.3
HDAI supported
IDE up to
SATA
PCI Express
PCI
LAN
AC '97 3
HDAI 3
Target core at introduction
6/04
PCI Express x16
ICH
Target line at introduction
800/533 MHz
DDR2 533/400, DDR 400/333
Celeron
Celeron D
0.09 m
m PGA 478/LGA 775
Celeron /P4
Celeron D/Prescott without EM64T
0.09 m
LGA 775
The max. memory of the 910GL is restricted only to 2 GB.
A GbE controller can be attached via the PCI Express x1 link providing 10/100/1000 Mbit/s speeds (e.g. Intel's 82571EB dual channel
GbE controller).
The Intel High Definition Audio Interface (HDAI) shares pins with the AC '97 link, so these interfaces cannot be operated concurrently.
Supports processors also in socketm PGA 478.
Figures 5.10: Main features of Intel’s 915xx family of chipsets
5.2 Desktop chipsets (8)
P4
Prescott
FSB 533/800 MHz
VGA1
PCI E. x16
915xx 1
(G)MCH
PCI E. x162
SDRAM
interface
SDRAM
SDRAM
interface
SDRAM
Max. 4 GB
DDR 333/400, DDR2 400/533
unbuffered, no ECC
DMI
MbE
MbE c.
PCI v.2.3
(2-4 slots)
GbE
GbE c.
LAN 10/100
PCI v.2.3
Ultra ATA/100
(1 port)
PCI E. x1
SATA
(4 ports)
ICH6
PCI E. x1
(1-2 ports)
GPIO
USB 2.0
(8 ports)
Audio
CODEC
AC'97 v.2.3
LPC
FWH
SIO
FD
KB
MS
SP
PP
1
The chipsets including the letter G in their designation provide an integrated VGA controller.
2
The 915GL/GV chipsets don't offer a PCI Express x16 interface.
Figure 5.11: Typical configuration of a value/desktop motherboard based on Intel’s 915xx family of chipsets
5.3 Overview of DP server and workstation chipsets
5/01
Cores
Foster
FSB
HT
EM64T
Socket
2/02
Prestonia-A
11/02
Prestonia-B
7/03
Prestonia-C
400 MHz
400 MHz
HT
533 MHz
HT
533 MHz
HT
mPGA 603
mPGA 603
mPGA 603
m PGA 603
Chipsets
6/04
Nocona
800 MHz
HT
EM64T
m PGA 604
8/04
DP-servers
2/02
E7500
11/02
E7501
E7320
8/04
E7520
DP-workstations
5/01
860
6/04
11/02
E7525
E7505
Figure 5.12: Intel’s chipsets designed for P4-based DP-servers and workstations
5.4 DP server chipsets (1)
5/01
Features
MCH
HT support
Nr. of mem. channels
Memory
Max. memory
E75xx/E73xx family
860
HT supported
Dual channel SDRAM
(registered, ECC)
Dual channel
RDRAM
16 GB 1
4 GB
Memory protection
ECC (opt.)
FSB
400 MHz
400 MHz
800 MHz
EM64T supported
533 MHz
EM64T support
PC 800/600
DRAM speed
DDR 266 /200
DDR 200
11/02
2/02
Aim
DP WS
Graphics interface up to
AGP 4X
Additional high speed if.
2x HI
RAS/RASUM
DP server
E7501
E7505
(Placer)
DP server
DP WS
6/04
8/04
8/04
1
2
E7320
E7520
E7525
(Lindenhurst-VS)
(Lindenhurst)
(Tumwater)
DP server
DP WS
DP server
PCI Express x16
AGP 8X
3x HI 2.0
RASUM 4
ICH
11/02
(Plumas)
E7500
DDR 333
DDR2 400
DDR 333/266
DDR2 400
ICH2:
ICH3-S:
Ultra ATA/100
Ultra ATA/100
3x HI 2.0
1x HI 2.0
4
4
RASUM
RAS
ICH3-S:
ICH4:
1x PCI Express x8
RASUM 4
4
3x PCI Express x8
RASUM
3
4
1x PCI Express x8
RASUM 4
ICH5R:/6300ESB:
ICH5R:/6300ESB:3
ICH5R:/6300ESB:3
Ultra ATA/100
Ultra ATA/100
Ultra ATA/100
SATA 1.0a
SATA 1.0a
SATA 1.0a
4
IDE up to
Ultra ATA/100
Ultra ATA/100
SATA
PCI
PCI 2.2
PCI 2.2
PCI 2.2
PCI 2.2
PCI-X
PCI 2.3/PCI 2.2
PCI 2.3/PCI 2.2
PCI 2.3/PCI 2.2
/PCI-X 2.2
/PCI-X 2.2
/PCI-X 2.2
PCI Express x1
USB
USB 1.1
LAN
10/100 Mbit/s
AC' 97
Target cores at introduction
Technology/Socket
1
2
3
4
USB 1.1
10/100 Mbit/s
AC '97 2.1
AC '97 2.2
Foster
Prestonia-A
0.18m/m PGA 603
USB 1.1
USB 2.0
USB 2.0
USB 2.0
10/100 Mbit/s
10/100 Mbit/s
10/100 Mbit/s
10/100 Mbit/s
AC '97 2.2
AC '97 2.3
Prestonia-B
0.13m/m PGA 603
AC '97 2.2/AC '97 2.3
AC '97 2.2/AC '97 2.3
USB 2.0
10/100 Mbit/s
AC '97 2.2/AC '97 2.3
Nocona
0.09m/m PGA 604
The 7505 supports also unbuffered DDR SDRAMs.
The 7520 includes an integrated four channel DMA engine in contrast to the E7320.
The ICH5R incorporates a RAID controller (Redundant Arrays of Indepentdent Disks) that utilizes the dual SATA ports for a high-performance RAID Level 0 configuration.
Reliability, Availability, Serviceability, Usability, Manageability
Figure 5.13: The evolution of Intel’s chipsets designed for P4 Xeon-based dual processor (DP) servers and workstations (WS)
5.4 DP server chipsets (2)
P4
Xeon
P4
Xeon
FSB
HI 2.0/PCI E. x8
MCH
High speed if.
HI 2.0/PCI E. x8
HI 2.0/PCI E. x8
5
1
SDRAM
interface
SDRAM
SDRAM
interface
SDRAM
Max. 8-32 GB
DDR 200/266/333/400, DDR2 400
2
with RASUM
(E7500/7501/73203 /7520)
registered, ECC
HI 1.5
ICH3-S
ICH5R
6300ESB6
6x v2.2
6x v2.3
4x v2.2
PCI
4x v.2.2
PCI-X
ATA/100
6
ICH5R
2
2
2
25
26
SATA
PCI Express x1
5
ICH3-S
6300ESB
ICH
LAN 10/100
6x v1.1
8x v2.0
4x v2.0
v2.2
v2.3
v2.2
USB
AC' 97
GPI0
5
(ICH3-S/5R /6300ESB)
LPC
HDAI
E7500
E7520
E7500
E7320
FWH
E7501
E7501
BIOS
2
The 16-bit HI 2.0 link is used to add PCI/PCI-X bridges (6700PXH), while the PCI Express x8 links are usually configured as two independent x4 ports,
each providing the possibility to add a PCI/PCI-X brigde (e.g. 6700PXH) or a dual GbE controller
Reliability, Availability, Serviceability, Usability, Manageability
3
The E7320 has only a single PCI Express x8 high speed interface
1
4
An external SATA controller is needed only in connection with the ICH3-S
5
The ICH5R includes an integrated RAID controller that utilizes the dual SATA ports for a high performance RAID Level 0 implementation
The 6300ESB SATA supports soft RAID.
6
Figure 5.14: The evolution of DP-server chipsets of P4 cores
E7520
E3520
5.4 DP server chipsets (3)
P4
Prestonia
P4
Prestonia
FSB 400/533 MHz
PCI-X v.2.2
(1-2 slots)
HI 2.0
GbE
GbE c.
E7500/E7501
PCI-X
bridge
SATA
SCSI
HI 2.0
MCH
HI 2.0
(with RASUM)
SATA c.
SDRAM
interface
SDRAM
SDRAM
interface
SDRAM
8/12/16 GB
DDR 200/266
registered, ECC opt.
SCSI c.
HI 1.5
PCI-X v.2.2
(1-2 slots)
SVGA
Video c.
MbE
MbE c.
PCI v.2.2
Ultra ATA/100
(2 ports)
ICH3-S
PCI v.2.2
(3 slots)
GPIO
USB v. 1.1
(5 ports)
LPC
FWH
SIO
FD
KB
MS
SP
PP
Figure 5.15: Typical configuration of a DP-server motherboard based on Intel’s E7500/E7501 chipsets
5.4 DP server chipsets (4)
P4
Nocona
P4
Nocona
FSB 800 MHz
PCI-X v.1.0b
(1 slot)
PCI E. x8
GbE
GbE c.
SCSI
SCSI c.
PCI-X
bridge
PCI E. x8
(or 2x x4)
PCI-X v.1.0b
(1-2 slot)
PCI E. x8
E7520
MCH
PCI E. x8
(with RASUM)
SDRAM
interface
SDRAM
SDRAM
interface
SDRAM
16/24/32 GB
DDR 266/333, DDR2 400
registered, ECC opt.
HI 1.5
SVGA
Video c.
PCI v.2.3
Ultra ATA/100
(2 ports)
PCI v.2.3
(0-1 slot)
SATA
(2 ports)
ICH5R
USB v. 2.0
(4 ports)
GPIO
AC' 97 v.2.3
LPC
FWH
SIO
FD
KB MS
SP
PP
Figure 5.16: Typical configuration of a DP-server motherboard based on Intel’s E7520 chipset (including the ICH5R)
5.5 DP workstation chipsets (1)
P4
Xeon
P4
Xeon
FSB
MCH
AGP 4X/8X/PCI E. x16
1
SDRAM
interface
Max. 16 GB
DDR 200/266/333, DDR2 400
SDRAM
2
with RASUM
SCSI
SATA
GbE
PCI-X
HI 2.0, PCI E x8
bridge
(860
2,3
/E7505/7525)
SDRAM
interface
registered, ECC opt.
SDRAM
HI 1.5
4
5
ICH2
ICH4
ICH5R
6300ESB
6x v2.2
6x v2.2
6x v2.3
4x v2.2
4x v.2.2
ICH2
PCI
6x v2.0
8x v2.0
4x v2.0
v2.1
v2.3
v2.3
v2.2
2
2
PCI-X
PCI Express x1
4x v1.1
ATA
ICH4
ICH
SATA
4
ICH5R
6300ESB 5
2
2
24
25
E7525
E7525
LAN 10/100
USB
(ICH2/4/5R/6300ESB)
AC' 97
GPI0
LPC
HDAI
860
860
E7505
E7525
E7525
FWH
BIOS
1
2
3
4
5
Reliability, Availability, Serviceability, Usability, Manageability
The first chipsets of this line (the 860) worked with DRDRAMs while using PC 600/800.
The MCH of the 860 provides two 16-bit high speed interfaces, to add PCI v2.2 bridges (P64H).
The ICH5R includes an integrated RAID controller that utilizes the dual SATA ports for a high performance RAID Level 0 implementation
The 6300ESB SATA supports soft RAID.
Figure 5.17: The evolution of DP-workstation chipsets of P4 cores
E7505
5.5 DP workstation chipsets (2)
P4
Prestonia B/C
PCI-X v.2.2
(1-2 slots)
GbE
SATA
FSB 533 MHz
GbE c.
SATA c.
PCI-X
HI 2.0
E7505
bridge
SCSI c.
SDRAM
interface
SDRAM
SDRAM
interface
SDRAM
MCH
AGP 8x
SCSI
P4
Prestonia B/C
(with RASUM)
PCI-X v.2.2
(1-2 slots)
8/12 GB
DDR 200/266
registered, ECC opt.
HI 1.5
MbE
MbE c.
PCI v.2.2
Ultra ATA/100
(2 ports)
PCI v.2.2
(1-2 slots)
ICH4
USB 2.0
(4 ports)
GPIO
Audio
CODEC
AC'97 v.2.2
LPC
FWH
SIO
FD
KB MS
SP
PP
Figure 5.18: Typical configuration of a DP-workstation motherboard based on Intel’s E7505 chipset
5.5 DP workstation chipsets (3)
P4
Nocona
P4
Nocona
FSB 800 MHz
PCI E. x16
x4
GbE c.
GbE c.
PCI-X
PCI-X
bridge
SDRAM
interface
E7525
MCH
PCI E. x8
x4
SDRAM
(with RASUM)
interface
SDRAM
16/24/32 GB
DDR 266/330
registered, ECC opt.
SDRAM
HI 1.5
GbE
GbE c.
PCI-X v.2.2
PCI v.2.2
(1-2 slots)
Ultra ATA/100
(2 ports)
ICH
PCI-X v.2.2
(2 slots)
USB 2.0
(4 ports)
Audio
CODEC
SATA
(2 ports)
6300ESB
GPIO
AC'97 v.2.2
LPC
SIO
FWH
FD
KB MS
SP
PP
Figure 5.19: Typical configuration of a DP-workstation motherboard based on Intel’s E7525 chipset
5.6 Intel’s 975X chipset
Figure 5.20: Intel’s 975X chipset for dual core processors
Source: Intel.com/products/I/chipsets/975x
6. Bandwidth considerations (1)
Width
Peak aggregate bandwidth
FSB
64-bit
8 * f c Mbyte/s
SDRAM-interface
64-bit
8 * f SDRAM Mbyte/s
Figure 6.1: Main features of the FSB and SDRAM interfaces
6. Bandwidth considerations (2)
Use d in the ch ipse ts
HI 1.5
DMI
W idth
Pe ak aggre gate ban dwidth
All prior chipset s
8-bit
266 MByt e/s
910GL, 915xx, 925X, 925XE
4*1 bit
2000 MByte/s
Figure 6.2: Main features of MCH/ICH interfaces used in Intel’s P4-based chipsets
6. Bandwidth considerations (3)
Use d in the ch ipse ts
HI
860
C SA
PC I E. x8
Pe ak aggre gate ban dwidth
16-bit
533 MByt e/s
8-bit
266 MByt e/s
E7500/7501/7505
16-bit
1066 MByte/s
E7221/7320/7520/7525
8*1 bit
4000 MByte/s
848P /865xx/875P /E7210
HI 2.0
W idth
Figure 6.3: Main features of high speed MCH interfaces of Intel’s P4-based chipsets
6. Bandwidth considerations (4)
P4
Northwood B/C
FSB 400/533/800 MHz
2132
AGP 8x
865xx1
VGA
GbE c.
GbE
3200-6400
CSA (HI 1.5)
(GMCH)
266
HI 1.5
MbE c.
MbE
PCI v.2.3
SDRAM
interface
SDRAM
21323200
SDRAM
interface
SDRAM
4 GB
DDR 266/333/400
unbuffered, no ECC
266
133
PCI v.2.3
(3 slots)
21323200
2*100
Ultra ATA/100
(2 ports)
2*150
SATA
(2 ports)
ICH5
USB 2.0
(6-8 ports)
GPIO
Audio
CODEC
AC'97 v.2.3
1.4
~5
LPC
SIO
FWH
FD
KB
MS
SP
PP
Figure 6.4: Peak bandwidth values (Mbyte/s) in typical desktops, based on Intel’s 865xx chipsets
6. Bandwidth considerations (5)
P4
Prescott
FSB 533/800 MHz
PCI E. x16
VGA
PCI E. x16
8000
1
915xx
(G)MCH
PCI E. x16
8000
DMI
MbE c.
MbE
PCI v.2.3
(2-4 slots)
GbE c.
GbE
3200-6400
PCI v.2.3
PCI E. x1
26644264
SDRAM
interface
SDRAM
4 GB
DDR 333/400, DDR2 400/533
unbuffered, no ECC
1*100
Ultra ATA/100
(1 ports)
4*150
SATA
(4 ports)
500
500
USB 2.0
(8 ports)
60
AC'97 v.2.3
SDRAM
133
PCI E. x1
(1-2 ports)
CODEC
SDRAM
interface
2000
ICH6
Audio
26644264
1.4
GPIO
~5
LPC
FWH
SIO
FD
KB
MS
SP
PP
Figure 6.5: Peak bandwidth values (Mbyte/s) in typical desktops, based on Intel’s 915xx chipsets
6. Bandwidth considerations (6)
P4
Prestonia
FSB 400/533 MHz
PCI-X v.2.2
(1-2 slots)
HI 2.0
GbE
GbE c.
PCI-X
bridge
SATA
HI 2.0
3200-4264
1066 E7500/E7501 16002128
MCH
1066
SATA c.
HI 2.0
SCSI
P4
Prestonia
SCSI c.
1066
16002128
SVGA
Video c.
MbE
MbE c.
PCI v.2.2
SDRAM
SDRAM
interface
SDRAM
8/12/16 GB
DDR 200/266
registered, ECC opt.
(with RASUM)
HI 1.5
PCI-X v.2.2
(1-2 slots)
SDRAM
interface
266
133
LAN
Ultra ATA/100
(2 ports)
2*100
PCI v.2.2
(3 slots)
ICH3-S
GPIO
USB v. 1.1
(5 ports)
1.5
~5
LPC
SIO
FWH
FD
KB
MS
SP
PP
Figure 6.6: Peak bandwidth values (Mbyte/s) in typical DP-servers, based on Intel’s E7500/E7501 chipsets
6. Bandwidth considerations (7)
P4
Nocona
P4
Nocona
FSB 800 MHz
PCI-X v.1.0b
GbE
SCSI
PCI E. x8
GbE c.
PCI-X
bridge
SCSI c.
PCI E. x8
PCI E. x8
PCI-X v.1.0b
4000
4000
3200
E7520
21283200
SDRAM
interface
SDRAM
21283200
SDRAM
interface
SDRAM
MCH
4000
16/24/32 GB
DDR 266/333, DDR2 400
registered, ECC opt.
(with RASUM)
PCI E. x8
(or 2x x4)
HI 1.5
SVGA
Video c.
MbE
MbE c.
PCI v.2.3
266
133
LAN
PCI v.2.3
ICH5R
USB v. 2.0
(4 ports)
AC' 97 v.2.3
Ultra ATA/100
(2 ports)
2*100
SATA
(2 ports)
2*150
60
GPIO
~1.4
~5
LPC
SIO
FWH
FD
KB MS
SP
PP
Figure 6.7: Peak bandwidth values (Mbyte/s) in typical DP-servers, based on Intel’s E7520/ICH5R chipset
6. Bandwidth considerations (8)
P4
Prestonia B/C
P4
Prestonia B/C
PCI-X v.2.2
(1-2 slots)
GbE
SATA
FSB 533 MHz
GbE c.
PCI-X
bridge
HI 2.0
E7505
1066
SATA c.
MCH
AGP 8x
SCSI
4264
SCSI c.
2132
16002132
SDRAM
interface
SDRAM
16002132
SDRAM
interface
SDRAM
8/12 GB
DDR 200/266
registered, ECC opt.
(with RASUM)
PCI-X v.2.2
(1-2 slots)
HI 1.5
GbE
GbE c.
PCI v.2.2
266
133
Ultra ATA/100
(2 ports)
2*100
PCI v.2.2
ICH4
USB 2.0
(4 ports)
60
GPIO
Audio
CODEC
AC'97 v.2.2
1.4
~5
LPC
SIO
FWH
FD
KB
MS
SP
PP
Figure 6.8: Peak bandwidth values (Mbyte/s) in typical DP-workstations, based on the Intel’s E7505 chipset
6. Bandwidth considerations (9)
P4
Nocona
P4
Nocona
FSB 800 MHz
PCI E. x16
3.2-6.4
E7525
8000
21322664
SDRAM
interface
SDRAM
21322664
SDRAM
interface
SDRAM
MCH
PCI E. x8
4000
(with RASUM)
GbE c.
PCI-X v.2.2
133
PCI v.2.2
533
PCI-X v.2.2
USB 2.0
(4 ports)
registered, ECC opt.
266
HI 1.5
GbE
16/24/32 GB
DDR 266/333
60
2*100
Ultra ATA/100
(2 ports)
2*150
SATA
(2 ports)
6300ESB
ICH
GPIO
Audio
CODEC
AC'97 v.2.2
1.4
~5
LPC
SIO
FWH
FD
KB MS
SP
PP
Figure 6.9: Peak bandwidth values (Mbyte/s) in typical DP-workstations based on the Intel’s E7525 chipset
7. Special aspects of the implementation
7.1 Attaching the display
7.2 PCI-X bridges
7.3 Attaching MbE/GbE controllers
7.4 Attaching SCSI controllers
7.5 Implementation of ICHs
7.1 Attaching the display
P4
VGA
P4
MCH
ICH
P4
MCH
VGA
On-board
video c.
P4
VGA
Off-board
video c.
P4
AGP 4x/8x/
PCI E. x8/x16
MCH
PCI
32 bit/33 MHz
ICH
ICH
(mostly ATI Rage XL)
Typical use:
Value/mainstream desktops
with the letter G in their
designation (e.g. 845G/GL/GV)
Entry level servers based on the E7210
DP-servers
Entry level servers based on
the E7221
Value/mainstream desktops
excluding those with the letters
GL or GV in their designation
(e.g. 845GL/GV)
High end desktops/entry level
workstations
DP-workstations
Figure 7.1: Alternatives for attaching a display in P4-based motherboards
7.2 PCI-X bridges (1)
GbE
GbE c.
SATA
SATA c.
SCSI
SCSI c.
PCI-X
HI/HI2.0/PCI E.
PCI-X
bridge
Figure 7.2: Use of PCI-X bridges to attach dedicated controllers
7.2 PCI-X bridges (2)
PCI
32/64-bit
33/66 MHz
64
P64H
16
HI
Used in e.g. 860
HI 2.0
E7500/7501/7505
(82806AA)
64
1
PCI 2.2/PCI-X 1.0
P64H2
64
16
(82870P2)
1/4/8
1
PCI 2.3/PCI-X 1.0b
2
PXH-V
PCI E. 1.0a x1/x4/x8
64
(6702PXH)
1
PCI 2.3/PCI-X 1.0b
1
PCI 2.3/PCI-X 1.0b
1
2
1/4/8
4/8
64
2
PXH
64
E7221
(6700PXH)
PCI E. 1.0a x4/x8
E7320/7520/7525
4/8
The interface can be independently configured as either a PCI bus or a PCI-X bus running at 33/66
or 66/100/133 MHz resp.
The bridge can operate either in x4 or x8 mode.
Figure 7.3: PCI-X bridges used in Intel’s P4-based motherboards
7.3 Attaching MbE/GbE controllers (1)
P4
P4
MCH
MCH
HI 1.5
HI 1.5
1
MbE c.
LAN 10/100
PCI
ICH
P4
MbE c.
ICH
Examples
82562ET
82562EZ
845xx (opt.
or standard)
848P3
865xx 3
3
875P
915xx 4
Value/mainstream desktops
1
2
3
4
82550PM
82551QM
E7500/7501/75052
E7500/75012
E7210
Early DP servers/workstations
(Furthermore E7210)
The LAN 10/100 interface is also designated as the LCI interface (LAN Connect Interface).
The 82550PM or the 8255IQM is available in DP servers and workstations usually in addition to a GbE c.
As an exception some early E7500 based motherboards provide only one or two MbE controllers.
Most of the enlisted motherboards provide either a MbE controller attached to the LAN 10/100 interface
or a GbE controller attached to the CSA interface.
A few 915xx based Intel motherboards provide either a 82562EZ MbE controller or the Marvell 88E8050
PCI Express x1-based GbE controller.
Figure 7.4: Alternatives used to attach a MbE controller in Intel’s P4-based motherboards
7.3 Attaching MbE/GbE controllers (2)
P4
MCH
P4
GbE
GbE c.
GbE c.
PCI
PCI-X
CSA
MCH
GbE
GbE c.
PCI-X
P4
HI 2.0
MCH
brigde
MCH
HI 1.5
ICH
ICH
P4
P4
HI 1.5
HI 1.5
GbE
P4
HI 1.5
ICH
GbE
GbE c.
PCI-X
ICH
(6300ESB)
Examples
82540EM
845xx
E75011
E7205
82541GI
875P
915xx
925X
E7210
82541PI
82547EI
82547GI
4
848P
865xx4
875P4
5
82545EM
E7500/7501/7505
82546EB (D)
E7500/7501/7505
875P
E7210
2
82541GI
E7320/7525 (w/6300ESB)
82541PI
E7320/7525 (w/6300ESB)
82541GB
E7320/7525 (w/6300ESB) 3
E7221
E7520(w/ICH5R)
All categories
Mainstream desktops
Early DP servers/workstations
Advanced DP servers/workstations
(Furthermore the E7210)
1
Ususally in companion with a MbE controller such as the 82550PM or the 82551QM.
2
The 82541GI is used either in 32-bit/33MHz or 32-bit/66 MHz mode.
3
The 82541PI and the 8254GB is used in the 32-bit/33 MHz mode.
Most of the enlisted motherboards provide either a MbE controller attached to the LAN 10/100 interface or a GbE controller attached to the CSA interface.
Ususally in companion with a MbE controller such as the 82551QM.
4
5
Figure 7.5: Widely used alternatives to attach a GbE controller in Intel’s P4-based motherboards via legacy buses
3
7.3 Attaching MbE/GbE controllers (3)
P4
P4
PCI-X
MCH
GbE
GbE c.
PCI-X
bridge
P4
x4
P4
GbE
PCI E. x8
GbE c.
MCH
x4
DMI
x4
PCI E. x8
x4
HI 1.5
P4
MCH
HI 1.5
PCI E. x1
GbE c.
GbE c.
GbE c.
ICH
ICH
(ICH6/
ICH6R)
(ICH5R)
ICH
(ICH5/
6300ESB)
Examples
82570EI 1
2
(88E8050 )
3
(BCM5721 )
915GV
925X
2
3
E7520/E7525 (w/ICH5R)
E7221
Advanced single processor motherboards
1
82546GB (D)
Advanced DP servers/workstations
82571EB
E7320
E7520
E7525
Advanced DP servers/workstations
Used to date (2/05) in Commel's FS-979 motherboards.
From Marvell
From Broadcom
Figure 7.6: Alternatives used to attach a GbE controller inIntel’s P4-based motherboards via the PCI Express bus
7.4 Attaching SCSI controllers
P4
P4
FSB
HI 2.0
PCI-X
bridge
SCSI c.
MCH
(E7500/7501)
(P64H2)
PCI-X
P4
PCI E. x8
SCSI c.
PCI-X
PCI-X
bridge
(PXH-V)
x8
P4
P4
FSB
MCH
(E7320)
P4
FSB
PCI E. x8
SCSI c.
PCI-X
bridge
PCI-X
(PXH)
MCH
(E7520)
ICH
ICH
ICH
Typical use:
LSI Logic 53C1020
(Ultra 320, single channel)
Adaptec A16-7899W
(Ultra 160, dual channel)
Adaptec AIC-7901
(Ultra 320, single channel)
Adaptec AIC-7902
(Ultra 320, dual channel)
Early DP-servers
Advanced mid-range DP-servers
Adaptec AIC-7902
(Ultra 320, dual channel)
LSI Logic 53C1030
(Ultra 320, dual channel)
Advanced high-end DP-servers
Figure 7.7: Alternatives used to attach a SCSI controller in Intel’s P4-based motherboards
Remark: A few entry-level servers and DP-workstations incorporate also a SCSI controller,
like some based on the E7221 or E7505 chipsets
7.5 Implementation of ICHs (1)
to (G)MCH
HI 1.5
8-bit/66 MHz*4
Multiplexer
PCI Bus 0
32-bit/33 MHz
USB 2.0
(2 ports)
D:29, F0
USB UHCI c. #1
USB 2.0
(2 ports)
D:29, F1
USB UHCI c. #2
USB 2.0
(2 ports)
D:29, F2
USB UHCI c. #3
PCI Bus 1
32-bit/33 MHz
D:8, F0
LAN 10/100
D:29, F7
USB 2.0 EHCI c.
D:30, F0
HUB/PCI bridge
PCI
(6 master)
ICH4
D:31, F0
LPC bridge
LPC
D:31, F1
ATA c.
ATA
(2 port)
D:31, F3
SMBus
SMBus
D:31, F5
AC'97 Audio c.
AC'97 v. 2.3
D:31, F6
AC'97 0 Modem c.
D: Device
F: Function
UHCI: Universal Host Controller Interface
EHCI: Enhanced Host Controller Interface
Figure 7.8: Simplified structure of the ICH4
LAN 10/100
7.5 Implementation of ICHs (2)
to (G)MCH
DMI
4*1-bit/2.5 GHz
Multiplexer
PCI Bus 0
32-bit/33 MHz
IHDA/AC'97 v.2.3
D27, F0
IHDA/AC'97 c.
PCI E. X1 v1.0a
D28, F0
PCI E. port 1
PCI E. x1 v1.0a
D28, F1
PCI E. port 2
PCI E. x1 v1.0a
D28, F2
PCI E. port 3
PCI E. x1. v1.0a
D28, F3
PCI E. port 4
USB 2.0
(2 ports)
D29, F0
USB UHCI c.
USB 2.0
(2 ports)
D29, F1
USB UHCI c.
USB 2.0
(2 ports)
D29, F2
USB UHCI c.
USB 2.0
(2 ports)
D29, F3
USB UHCI c.
D29, F7
USB 2.0 EHCI c.
PCI v.2.3
PCI Bus 1
32-bit/33 MHz
D8, F0
LAN 10/100
LAN 10/100
ICH6
D30, F0
PCI to PCI bridge
D30, F2
AC'97 Audio c.
AC'97/IHDA
D30, F3
AC'97 Modem c.
LPC
D31, F0
LPC c.
ATA
(1 port)
D31, F1
ATA c.
SATA
(4 port)
D31, F2
SATA c.
SMBus
D31, F3
SMBus c.
D: Device
F: Function
UHCI: Universal Host Controller Interface
EHCI: Enhanced Host Controller Interface
Figure 7.9: Simplified structure of the ICH6