Transcript Pengantar Organisasi Komputer

IKI10230
Pengantar Organisasi Komputer
Bab 7: Control Unit
Sumber:
1. Hamacher. Computer Organization, ed-5.
2. Materi kuliah CS152/1997, UCB.
28 Mei 2003
Bobby Nazief ([email protected])
Qonita Shahab ([email protected])
bahan kuliah: http://www.cs.ui.ac.id/kuliah/iki10230/
1
Pengendalian Eksekusi Instruksi:
Hardwired Control
2
Prosesor: Control & Datapath
Computer
Processor
(active)
Control
(“brain”)
Datapath
(“brawn”)
Memory
(passive)
(where
programs,
data
live when
running)
Devices
Input
Output
3
Review: Organisasi Prosesor (Single-bus)
Control lines
Address
lines
Memory
bus
Data
lines
PC
Instruction
Decoder
MAR
IR
MDR
R0
Control
Unit
Y
R(n-1)
ALU
control
lines
Add
Sub
Datapath
Unit
ALU
XOR
Carry-in
Z
TEMP
4
Interaksi Control  Datapath
Control
Conditions
IR
Instruction
MARin
ADD
PCout
Riin
Control
Signals
Datapath
STEP
CONTROL SIGNALS
1.
PCout, MARin, Read, Clear Y, Set carry-in to ALU, Add, Zin
2.
Zout, PCin, WMFC
3.
MDRout, IRin
4.
R3out, MARin, Read
5.
R1out, Yin, WMFC
6.
MDRout, Add, Zin
7.
Zout, R1in, End
5
Organisasi Unit Pengendali
Clock
CLK
Control Step
Counter
  

  
IR
Status
Flags
Decoder/
Encoder

Condition
Codes
  
Control Signals
6
Pemisahan Decoder & Encoder
Clock
CLK
Reset
Control Step
Counter
  
Step Decoder
T1 T2
  
Status
Flags

Instruction
Decoder
  
  
IR

LDI
LD
Tn
Condition
Codes
Encoder
INSn
Run
  
End
Control Signals
7
Contoh Struktur Encoder untuk sinyal Zin
° Fungsi Logika:
BR
ADD
T5
T6
Zin = T1 + T6  ADD + T5  BR + …
° Zin akan terjadi pada:
T1
 
 
• T1: untuk setiap instruksi
(instruksi berikut: PC+1)
• T5: untuk instruksi ADD
• T6: untuk instruksi BR
Zin
8
Interaksi Memori  [Control,Datapath]
Control
Ideal
Instruction
Memory
Instruction
Rd Rs
5
5
A
PC
32
32
Rw Ra Rb
32
Registers
B
Clk
Clk
Conditions
Rt
5
ALU
Next Address
Instruction
Address
Control Signals
32
Data
Address
Data In
Ideal
Data
Memory
Data
Out
Clk
Datapath
9
Pengendalian Eksekusi Instruksi:
Microprogrammed Control
10
Microprogramming
° Control is the hard part of processor design
° Datapath is fairly regular and well-organized
° Memory is highly regular
° Control is irregular and global
Microprogramming:
-- A Particular Strategy for Implementing the Control Unit of a
processor by "programming" at the level of register transfer
operations
Microarchitecture:
-- Logical structure and functional capabilities of the hardware as
seen by the microprogrammer
Historical Note:
IBM 360 Series first to distinguish between architecture & organization
Same instruction set across wide range of implementations, each with
different cost/performance
11
Microinstructions
WMFC
End
Zout, R1in, End
Read
7.
Add
MDRout, Add, Zin
Carry-in
6.
Clear Y
R1out, Yin, WMFC
Zout
5.
Zin
R3out, MARin, Read
R3out
4.
R1out
MDRout, IRin
R1in
3.
Yin
Zout, PCin, WMFC
MDRout
2.
MARin
PCout, MARin, Read, Clear Y, Carry-in to ALU, Add, Zin
PCout
1.
PCin
CONTROL SIGNALS
IRin
1
2
3
4
5
6
7
STEP
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
1
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
0
0
1
0
0
0
0
1
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
1
0
1
0
0
1
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
1
12
PCin
PCout
MARin
MDRout
Yin
R1in
R1out
R3out
1
2
3
4
5
6
7
IRin
Organisasi Microprogrammed Control Unit
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
1
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
0
IR
Starting
Address
Generator
Clock
μPC
0
1
0
0
0
0
1
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
1
0
1 0 0
Control
0Store
1 0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
1
Control
Word
13
Organisasi μProgrammed Control Unit: Branching
Status Flags
Addr.
IR
Starting
Address
Generator
Clock
μPC
Condition Codes
Microinstruction
0
PCout, MARin, Read, Clear Y, Carry-in to ALU, Add, Zin
1
Zout, PCin, WMFC
2
MDRout, IRin
3
Branch to starting addr. of appropriate μroutine
…………………………………………………………………………….
25
PCout, Yin, if N=0 then branch to μinstruction 0
26
Offset-field-of-IRout, Add, Zin
27
Zout, R1in, End
Control
Store
Control
Word
14
Encoding of Microinstruction
F1
F2
F3
F4
(4 bits)
(3 bits)
(3 bits)
(4 bits)
0000: No transfer
000: No transfer 000: No transfer 0000: ADD
0001: PCout
001: PCin
001: MARin
0001: SUB
0010: MDRout
010: IRin
010: MDRin
.
0011: Zout
011: Zin
011: TEMPin
.
0100: R0out
100: R0in
100: Yin
.
0101: R1out
101: R1in
1111: XOR
° Most signals are not needed simultaneously
° Many are mutually exclusive:
•
ALU: 1 function at a time
•
Data source is unique
° Organization:
•
Vertical Organization (Highly Encoded μInstruction)
•
Horizontal Organization (otherwise)
15
Microprogram Sequencing: Branching Implementation
° 1 Machine Instruction  1 Set of μInstructions
• large total number of μInstruction
• large Control Store
° Many Addressing Modes  many instruction
combinations
• results in many duplications of common parts
° If the common parts are to be shared  many
branches
• results in longer execution time
Need efficient branching techniqe  Bit-ORing
16
Microprogram Sequencing (1/2): Add src,Rdst
000
MAR  [PC]; Read; Z  [PC]+1
Start
001
PC  [Z]; WMFC
002
IR  [MDR]
003
Branch[InstDec,OR]
Indexed
Autodecrement
161
MAR  [PC]; Read;
Z  [PC]+1
162
PC  [Z]; WMFC
121
141
Z  [Rsrc] - 4
142
MAR, Rsrc  [Z];
Read
Register indirect
Autoincrement
MAR  [PC]; Read;
Z  [PC]+1
122
Z  [Rsrc]
111
MAR  [Rsrc];
Read
112
Branch[171]; WMFC
17
Microprogram Sequencing (2/2): Add src,Rdst
Indexed
Autodecrement
143
Branch[170,OR];
WMFC
166
Branch[170,OR];
WMFC
Autoincrement
123
Branch[170,OR];
WMFC
Register indirect
112
Branch[171];
WMFC
170
MAR  [MDR]; Read; WMFC
171
Y  [MDR]
172
Z  [Y] + [Rdst]
173
Rdst  [Z]
End
18
Branching in Microinstruction: Add (Rsrc)+,Rdst
Mode
11 10
ADD
Rdst
Rsrc
0 1 0
OP code
8 7
4 3
0
Addr.
Microinstruction
000
PCout, MARin, Read, Clear Y, Set carry-in, Add, Zin
001
Zout, PCin, WMFC
002
MDRout, IRin
003
μBranch {μPC  101; μPC5,4  [IR10,9]; μPC3  [IR10].[IR9].[IR8]}
121
Rsrcout, MARin, Read, Clear Y, Set carry-in, Add, Zin
122
Zout, Rsrcin
123
μBranch {μPC  170; μPC0  [IR8]}, WMFC
170
MDRout, MARin, Read, WMFC
171
MDRout, Yin
172
Rdstout, Add, Zin
173
Zout, Rdstin, End
IR10,9 = 01 (autoincrement)
IR8 = 0 (direct)
Bit
ORing
19
Microinstruction Sequencing: Organization
IR
Status Flags
Condition Codes
Decoding Circuits
μAR
Control
Store
μIR
Next Address
μInstruction Decoder
  
Control Signals
20
Encoding of Microinstruction w/ Next Address
F0
F1
F2
(8 bits)
(3 bits)
(3 bits)
Address of next
microinstruction
F4
(4 bits)
0000: ADD
0001: SUB
.
F3
(3 bits)
000: No transfer
000: No transfer 000: No transfer
001: PCout
001: PCin
001: MARin
010: MDRout
010: IRin
010: MDRin
011: Zout
011: Zin
011: TEMPin
100: Rsrcout
100: Rsrcin
100: Yin
101: Rdstout
101: Rdstin
...
F8
F9
F10
(1 bit)
(1 bit)
(1 bit)
0: NextAdrs 0: No
0: No
action
action
1: InstDec
1: ORmode 1: ORindsrc
.
1111: XOR
21
Content of μStore
F0
000
001
002
003
121
122
170
171
172
173
0
0
0
0
1
1
1
1
1
0
0
0
1
0
2
7
7
7
7
0
F1
1
2
1
0
2
0
1
2
3
0
0
0
0
0
1
0
0
0
1
0
0
1
1
0
0
1
1
1
0
1
F2
1
1
0
0
0
1
0
0
1
1
0
0
0
0
0
1
0
0
0
1
1
0
1
0
1
0
0
0
1
0
F3
1
1
0
0
1
0
0
0
1
1
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
F4
1
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
1
0
0
0
F
6
F
7
F
8
F
9
F
1
0
1
0
0
0
1
0
0
0
0
0
0
1
0
0
0
1
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
22
/Etc
23
“Macroinstruction” Interpretation
Main
Memory
ADD
SUB
AND
.
.
.
DATA
execution
unit
CPU
control
memory
User program
plus Data
this can change!
one of these is
mapped into one
of these
AND microsequence
e.g., Fetch
Calc Operand Addr
Fetch Operand(s)
Calculate
Save Answer(s)
24
Control: Hardware vs. Microprogrammed
° Control may be designed using one of several initial representations.
The choice of sequence control, and how logic is represented, can then
be determined independently; the control can then be implemented with
one of several methods using a structured logic technique.
Initial Representation
Sequencing Control
Logic Representation
Implementation Technique
Finite State Diagram
Microprogram
Explicit Next State
Function
Microprogram counter
+ Dispatch ROMs
Logic Equations
Truth Tables
PLA
ROM
“hardwired control”
“microprogrammed control”
25