Transcript TI1400 Computer Organization at TU Delft

Basic Processing Unit
(Chapter 7)
http://www.pds.ewi.tudelft.nl/~iosup/Courses/2011_ti1400_7.ppt
Problem: How to Implement Computers?
Lectures
3,4,5,6
Lecture 2
Lecture 1
Computers
Programmable Devices
Circuit Design
Data representation,
conversion, and op.
Instruction repr. and
use
Memory organization
Program sequencing
von Neumann archi.
Instruction levels
Digital logic
Memory elements
Other building blocks
(Multiplexer,Decoder)
Finite State Machines
2
Why Computer
History of Computing
TU-Delft
(1642-2011)
Lecture 0 Organization Matters?
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Problem
instruction
?
y
Decoder
ALU
a
f
y
Reg
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Lecture 2
Von Neumann Architecture
Memory
X: 1
Y: 2
Z: 3
•
•
READ(X)
READ(Y)
ADD(X,Y,Z)
WRITE(Z)
(Central) Processing Unit
TEMP_A:
TEMP_B:
RESULT:
IR:
arithmetic
unit
CONTROL
Input
Output
PC:
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The Processing Unit
1. Basic Processing Cycle
2. Types of Operations
3. Control Mechanisms
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Basic Processing Cycle
• Assume an instruction occupies a 32 bit single word
in byte addressable memory
• Basic cycle to be implemented:
1. Fetch instruction pointed to by PC and
put it into the Instruction Register (IR): [IR]  M([PC])
2. Increment PC: [PC]  [PC] + 4
3. Perform actions as specified in IR
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Organization
PC
MAR
memory bus
MDR
Y
ALU
Z
CPU bus
Decoder
control
IR
Register file
R0
R1
R2
Rn-1
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Register gating
CPU bus
Y_in
Const 4
Y
Select
x
x
Ri
MUX
x
ALU
Z_in
Ri_in
x
Ri_out
Z
x
Z_out
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Register gating
Edge-triggered D flip-flop
Multiplexer
R1_in
R2_in
1 0
I
R/W
C
I
R/W
I
R/W
C
C
C
R3_in
C
D
Q
C
D
D
Q
Q
R1_out
R2_out
R3_out
1 bit of common bus line
Tri-state gate: high impedance iff Ri_out=0, Q iff Ri_out=1
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Multiple Datapaths
Bus A
R0
Y
R1
R2
R3
ALU
Bus C
register file
Bus B
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The Processing Unit
1. Basic Processing Cycle
2. Types of Operations
1.
3. Control Mechanisms
2.
3.
4.
5.
6.
Register Transfer
Fetch from Memory
Store to Memory
Arithmetic/Logic Ops.
Complete Example
Branching Ops.
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2. Types of Operations
• Operation cycle includes:
- Transfer data from register to register or to ALU
- Fetch contents of memory location and put in
one of the CPU registers
- Store contents of CPU register in memory
location
- Perform arithmetic or logic operation
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2.1. Register Transfers
Copy contents of R1 to R3
R_out
CPU bus
1.
2.
3.
4.
Address_out=R1
R_out
Address_in=R3
R_in
1. R1_out
2. R3_in
R0
Y
R1
R2
ALU
R3
Z
register file
R_in
Address_out
Address_in
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2.2. Fetch from Memory (1)
Memory bus
Data lines
Internal
processor bus
MDR_out
MDR_outE
x
x
MDR
x
MDR_inE
x
MDR_in
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2.2. Fetch from memory (2)
e.g., Move (Ri),Rj
Control Step 1
Control Step 2
Control Step 3
1.
2.
3.
4.
5.
MAR  [Ri]
Start read on memory bus
Wait for MFC response
Load MDR from memory bus
Rj  [MDR]
MAR
Address
MDR
Data
Memory
Read
Memory Function
Complete
CPU
MFC
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Fetch from memory (3)
Control Step 1.
Control Step 2.
Control Step 3.
Signal Activation Sequence
Ri_out, MAR_in, Read
MDR_inE, WMFC
MDR_out, Rj_in
Internal
processor bus
Ri_in
x
MDR_outE
Memory bus
Data lines
MDR_out
x
x
MDR
x
MDR_inE
Ri
x
x
Ri_out
MDR_in
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2.2. Fetch from Memory (4)
Timing of the Operation
1
2
1. Ri_out, MAR_in, Read
2. MDR_inE, WMFC
3. MDR_out, Rj_in
3
CLK
MAR_in
address
Read
MR
MDR_inE
Data
MFC
MAR to Mem.Bus
New Address
Mem.Read Cmd.
Value
Mem.Bus to MDR
Mem.Fnc.Complete
MDR_out
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2.3. Store to Memory
e.g., Move Rj,(Ri)
1.
2.
3.
Ri_out, MAR_in
Rj_out, MDR_in, Write
MDR_outE, WMFC
Address
Memory
Data
CPU
Write
MFC
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2.4. Arithmetic Operation
ADD R3,R2,R1
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Step
1.
Action
Address_out  R1
Y_in
R_out
2.
Address_out  R2
R_out
F_alu  “ADD”
Z_in

Address_in  R3
Z_out
R_in
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1.
Register Transfers
CPU bus
Y_in
Y
ALU
Z
Address_out  R1
Y_in
R_out
R_out
R0
R1
R2
R3
register file
Address_out
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Arithmetic Operation
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ADD R3,R2,R1
Step
1.
Action
Address_out  R1
Y_in
R_out
2.
Address_out  R2
R_out
F_alu  “ADD”
Z_in

Address_in  R3
Z_out
R_in
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2.
Register Transfers
CPU bus
Y_in
F_alu
Z_in
Y
ALU
Z
Address_out  R2
R_out
F_alu  “ADD”
Z_in
R_out
R0
R1
R2
R3
register file
Address_out
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Arithmetic Operation
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ADD R3,R2,R1
Step
1.
Action
Address_out  R1
Y_in
R_out
2.
Address_out  R2
R_out
F_alu  “ADD”
Z_in

Address_in  R3
Z_out
R_in
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
Register Transfers
Address_in  R3
Z_out
R_in
CPU bus
R0
Y
R1
R2
ALU
R3
Z
Z_out
register file
R_in
Address_in
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Steps in time
Step
Y_in
1
2
CPU bus
3
Y_in
ALU
Z_in
Z_in
Z_out
R_in
Y
Z
Z_out
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The Processing Unit
1. Basic Processing Cycle
2. Types of Operations
1.
3. Control Mechanisms
2.
3.
4.
5.
6.
Register Transfer
Fetch from Memory
Store to Memory
Arithmetic/Logic Ops.
Complete Example
Branching Ops.
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2.5. Execution of a Complete Instruction
1.
2.
3.
4.
Fetch instruction
Fetch the operand
Perform operation
Store result
• Example ADD (R3),R1
[R1]  M([R3]) + [R1]
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Execution fetch (1)
Step
1
Step 1-3:
Action
PC_out, MAR_in, Read Instruction fetch
and PC update
Set carry-in ALU
F_alu = “ADD”
Z_in

Z_out, PC_in
Wait for MFC
[PC]  [PC ]+1
3
MDR_out, IR_in
[IR]  M([PC ])
Note: for architectures having PC:=PC+4
a different scheme must be used
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Fetch instruction
Q Why MAR_in?
MAR_in
1. PC_out, MAR_in, Read
Set carry-in ALU
F_alu = “ADD”
Z_in
MAR
PC_out
PC
ADD
ALU
Z_in
Z
carry
IR
MDR
Read
WFMC
Q Why Set carry-in ALU?
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Execution fetch (2)
Step 1-3:
instruction
fetch
and PC
update
Step
1
Action
PC_out, MAR_in, Read
Set carry-in ALU
F_alu = “ADD”
Z_in

Z_out, PC_in
Wait for MFC
[PC]  [PC ]+1
3
MDR_out, IR_in
[IR]  M([PC ])
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Fetch instruction
MAR_in
PC_in
 Z_out, PC_in
Wait for MFC
MAR
PC
IR
ALU
MDR
MDR_in
Z
Read
WFMC
Z_out
Q What is read into MDR?
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Execution fetch (3)
Step 1-3:
instruction
fetch
and PC
update
Step
1
Action
PC_out, MAR_in, Read
Set carry-in ALU
F_alu = “ADD”
Z_in

Z_out, PC_in
Wait for MFC
[PC ]  [PC ]+1
3
MDR_out, IR_in
[IR]  M([PC ])
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Fetch instruction
MAR
3. MDR_out, IR_in
Q What is loaded into IR?
PC
IR
ALU
MDR
IR_in
Z
Read
WFMC
MDR_out
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Execute
Step
4
Action
Address_out=R3, R_out
MAR_in
Step 4 and 5:
Read
operand fetch

Address_out=R1, R_out
Y_in, Wait for MFC
6
MDR_out, Z_in
F_alu = “ADD”
Perform
addition
7
Address_in=R1, R_in
Z_out, End
Store
Result
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Q Role of Decoder? 4. R3_out
MAR_in
CPU bus
Read
Execute
Read
PC
MAR
memory bus
MDR
Y
ALU
Decoder
control
IR
register file
R0
R1
R2
R3
Z
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Execute
Step
4
Action
Address_out=R3, R_out
MAR_in
Step 4 and 5:
Read
operand fetch

Address_out=R1, R_out
Y_in, Wait for MFC
6
MDR_out, Z_in
F_alu = “ADD”
Perform
addition
7
Address_in=R1, R_in
Z_out, End
Store
Result
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Execute
Q Where does MDR
read from?
CPU bus
WFMC
PC
MAR
memory bus
 R1_out
Y_in, Wait for MFC
Decoder
control
IR
MDR
Y
ALU
Z
R0
R1
R2
R3
register file
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Execute
Step
4
Action
Address_out=R3, R_out
MAR_in
Step 4 and 5:
Read
operand fetch

Address_out=R1, R_out
Y_in, Wait for MFC
6
MDR_out, Z_in
F_alu = “ADD”
Perform
addition
7
Address_in=R1, R_in
Z_out, End
Store Result
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Execute
Q Who sets F_alu to ADD? 6. MDR_out, Z_in
F_alu = “ADD”
CPU bus
PC
MAR
memory bus
MDR
Y
Q Why Z_in?
ALU
Decoder
control
IR
register file
R0
R1
R2
R3
Z
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Execute
Step
4
Action
Address_out=R3, R_out
MAR_in
Step 4 and 5:
Read
operand fetch

Address_out=R1, R_out
Y_in, Wait for MFC
6
MDR_out, Z_in
F_alu = “ADD”
Perform
addition
7
Address_in=R1, R_in
Z_out, End
Store
Result
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Q Role of End? 7. R1_in
Z_out, End
CPU bus
Execute
PC
MAR
memory bus
MDR
Y
ALU
Decoder
control
IR
register file
R0
R1
R2
R3
Z
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The Processing Unit
1. Basic Processing Cycle
2. Types of Operations
1.
3. Control Mechanisms
2.
3.
4.
5.
6.
Register Transfer
Fetch from Memory
Store to Memory
Arithmetic/Logic Ops.
Complete Example
Branching Ops.
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2.6. Branching
Jump PC+Offset
Step
1-3
Action
<instruction fetch
as in previous example>

PC_out, Y_in
5
Offset-field-IR_out
F_alu = “ADD”
Z_in
6
PC_in
Z_out, End
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 PC_out, Y_in
Branching
CPU bus
PC
MAR
memory bus
MDR
Y
ALU
Decoder
control
IR
register file
R0
R1
R2
R3
Z
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Branching
Step
1-3
Action
<instruction fetch
as in previous example>

PC_out, Y_in
5
Offset-field-IR_out
F_alu = “ADD”
Z_in
6
PC_in
Z_out, End
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Branching
CPU bus
PC
MAR
memory bus
MDR
Y
ALU
Z
5. Offset-field-IR_out
F_alu = “ADD”
Z_in
Decoder
control
IR
register file
R0
R1
R2
R3
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Branching
Step
1-3
Action
<instruction fetch
as in previous example>

PC_out, Y_in
5
Offset-field-IR_out
F_alu = “ADD”
Z_in
6
PC_in
Z_out, End
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Branching
CPU bus
PC
MAR
memory bus
6. PC_in
Z_out, End
Decoder
control
IR
MDR
Y
ALU
Z
R0
R1
R2
R3
register file
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Conditional branching
JN PC+Offset
Step
1-3
Action
<instruction fetch
as in previous example>

PC_out, Y_in
If N=0 then End
5
Offset-field-IR_out
F_alu = “ADD”
Z_in
6
PC_in
Z_out, End
If not Negative
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The Processing Unit
1. Basic Processing Cycle
2. Types of Operations
3. Control Mechanisms
Q Who sets F_alu to ADD?
1. Hardwired
2. Micro-Programmed
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3. Control Mechanisms
• There are two basic control organizations:
- Hardwired control
- Micro-programmed control
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The Processing Unit
1. Basic Processing Cycle
2. Types of Operations
3. Control Mechanisms
Q Who sets F_alu to ADD?
1. Hardwired
2. Micro-Programmed
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3.1. Hardwired Control
Control Unit Organization
CLK
Clock
Control step
counter
IR
Encoder/
Decoder
Status
Flags
Condition
Codes
Control signals
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3.1. Hardwired Control
Separating decoding/encoding
Clock
Q Role of Run?
Only one set to 1
IR
Control step
counter
Reset
Step decoder
T_n
T_1
Ins_1
Instruction
decoder Ins_n
Encoder
Run
Z_in
Status
Flags
Condition
Codes
End
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3.1. Hardwired Control
Generation of control signals
ADD
BRanch
T_6
T_5
T_1
Z_in = T_1 + T_6 . ADD + T_5 . BR
time slot
Z_in
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3.1. Hardwired Control
End signal
Other example:
End = T_7 . ADD + T_6 . BR +(T_6 . N + T_4 . /N) .BRN
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3.1. Hardwired Control
Performance
• Performance is dependent on:
- Power of instructions
- Cycle time
- Number of cycles per instruction
• Performance improvement by:
- Multiple datapaths
- Instruction prefetching and pipelining
- Caches
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Complete CPU
Instruction
unit
Integer
Integer
Integer
unit
unit
unit
Data
Cache
Instruction
Cache
Bus
Interface
Main
Memory
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Floating-point
Floating-point
Floating-point
unit
unit
unit
System Bus
Processor/CPU
Input/
Output
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3.2. Micro-programmed control
• All control bits are organized as memory
• Each memory location represents a control setting/word
- The word represents the state (0/1) of each control signal
• Memory words are called micro-instructions
• Micro-routines are sequences of micro-instructions
- Control store for all micro-routines
- Micro-program counter (uPC) to read control words sequentially
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3.2. Micro-Programmed Control
Examples of Micro-Instructions
microinstruction
PC_in MAR_in Addr_in
Z_in
...
1
2
3
..
..
0
1
0
1
0
0
...
...
...
1
0
0
00
00
01
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3.2. Micro-Programmed Control
Example of a Micro-routine
Address
Micro-instruction
0
PC_out, MAR_in, Read, Set carry-in ALU, F_alu = “ADD”, Z_in
1
Z_out, PC_in, Wait for MFC
2
MDR_out, IR_in
Fetch Instruction
3
Branch to starting address routine (here, 25)
........................................................................................................
25
PC_out, Y_in, if N=0 then goto address 0
Test N bit
26
Offset-field-of-IR_out, F_alu = “ADD”, Z_in
27
Z_out, PC_in, End
New PC address
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3.2. Micro-Programmed Control
Basic organization
Q Can this organization perform conditional branching
operations?
Starting
address
IR
generator
Clock
micro-PC
Control
Store
Control
Signals
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3.2. Micro-Programmed Control
Detailed organization
IR
Clock
Starting/
Branching
address
generator
Status flags
Control codes
micro-PC
Control
Store
Control
Signals
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3.2. Micro-Programmed Control
micro-PC Operation
• Micro-PC is incremented by 1, except:
- After loading IR
• Micro-PC is set to first micro-instruction for
executing machine instruction
- At End
• Micro-PC is set to first micro-instruction of
instruction fetch routine (typically 0)
- At Branch instruction
• Micro-PC is set to the branch address
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3.2. Micro-Programmed Control
Why micro-programming?
• Flexibility
- emulation of different instruction sets on same
hardware
• Support for powerful instructions
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3.2. Micro-Programmed Control
Structure micro-instructions
• Most simple organization: 1 bit per control
signal
• However,
- Many bits needed (e.g., 80-120 bits)
- For many signals, only one is needed per cycle;
hence they can be grouped
- Coding is possible: e.g., an address instead of a
single control bit per register
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3.2. Micro-Programmed Control
Example
F1
F2
Field 1(4
Field 2(4
Field 3(4
Field 4(4
Field 5(2
Field 6(1
Field 7(1
Field 8(1
............
F3
bits):
bits):
bits):
bits):
bit) :
bit) :
bit) :
bit) :
F4
F5
F6
F7
F8
Register address_in
Register address_out
Other registers_in
Function ALU
Read/Write/Nop
Carry-in ALU
WMFC
End
..............
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3.2. Micro-Programmed Control
Forms of organization
• Little coding: horizontal organization
- Large words
- Little decoding logic
- Fast
• Much coding: vertical organization
- Small control store
- Much decoding logic
- Slower
• Mixed organization
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3.2. Micro-Programmed Control
Horizontal/Vertical
F0 F1 F2 F3
Horizontal
R0 R1 R2 R3
F0 F1
Decoder
Vertical
R0 R1 R2 R3
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3.2. Micro-Programmed Control
Sequencing
• Thus far only branch after fetch
• No sharing of micro-code between micro-routines
• Micro-subroutines lead to more efficient control store
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3.2. Micro-Programmed Control
Multi-way branching
• Number of two-way branches
- disadvantage: slows down
• More than one branch address in micro-instruction
- disadvantage: more bits required
• bit-ORing if specified branch address
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3.2. Micro-Programmed Control
Example
branch
address
xxx00
micro-instruction
OR
yz
part of IR
xxxyz
actual
branch
address
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3.2. Micro-Programmed Control
Example microroutine (1)
ADD (Rsrc)+, Rdst
IR
OP code
Mode
010
11 10
8 7
Instruction Format
Rsrc
Rdst
4 3
0
bit 8:
direct/indirect
bit 9,10: indexed (11)
autodecrement(10)
autoincrement(01)
register(00)
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3.2. Micro-Programmed Control
Example microroutine (2)
Address
Micro-instruction
0
PC_out, MAR_in, Read, Set carry-in ALU, F_alu = “ADD”, Z_in
Z_out, PC_in, Wait for MFC
use bits from IR for
FETCH
2
MDR_out, IR_in
addressing mode
3
μBranch{μPC101 (from PLA); μPC_5,4[IR_10,9];
μPC_3{[not.IR_10].[not.IR_9].[IR_8]}
...........................................................................................................
121
Rsrc_out, MAR_in, Set carry-in ALU,Read, F_alu = “ADD”, Z_in
122
Z_out, Rscr_in
123
μBranch{μPC 170; μPC_0[not.IR_8]}, WMFC
170
171
direct 172
173
MDR_out, MAR_in, Read, WMFC
MDR_out, Y_in
Rdst_out, F_alu = “ADD”, Z_in
Z_out, Rdst_in, End
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autoincrement
indirect
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3.2. Micro-Programmed Control
Micro branch address
IR
OP code
Mode
010
Rsrc
11 10 9 8 7
Rdst
4 3
0
/IR10./IR9.IR8
PLA
101
0 0 1 0 1 0 0 0 1
121
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3.2. Micro-Programmed Control
Micro branch address
IR
OP code
Mode
010
11 10
Rsrc
8 7
Rdst
4 3
0
/IR8
PLA
170
0 0 1 1 1 10 0 1
171
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3.2. Micro-Programmed Control
Next-address field (1)
• Micro-instruction contains address next microinstruction
• Larger store needed
• Branch micro-instructions no longer needed
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Next-address field (2)
Status
flags
IR
Condition
codes
Decoding circuits
micro-AR
Control store
Next address
micro-IR
Microinstruction decoder
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3.2. Micro-Programmed Control
Example
F0
F1
F2
Field 0(8
Field 1(4
Field 2(4
Field 3(4
Field 4(4
Field 5(2
Field 6(1
Field 7(1
Field 8(1
............
F3
bits):
bits):
bits):
bits):
bits):
bit) :
bit) :
bit) :
bit) :
F4
F5
F6
F7
F8
Next address
Register address_in
Register address_out
Other registers_in
Function ALU
Read/Write/Nop
Carry-in ALU
WMFC
End
PLA/ORing etc
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3.2. Micro-Programmed Control
Emulation
• A micro-program determines the machine
instructions of a computer
• Suppose we have two computers M1 and M2 with
different instruction sets
• By adapting the micro-program of M1, we can
emulate M2
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3.2. Micro-Programmed Control
Organization
• Micro-program is often placed in ROM on CPU chip
• Some machines had writable control store, i.e. user
could change instruction set
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