Transcript Sisteme cu microprocesoare

Microprocessor-based systems
Course 6 Memory design
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Memory circuits
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Memory cell:
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Memory location (memory word)
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A digital circuit that memorize one bit (e.g.: flip-flop)
Set of elementary memory cells accessed (read or written)
simultaneously
The basic addressing element (1, 4, 8,16, 32 bits)
Every location has an address
Memory circuit = Set of memory locations
Memory capacity – total number of locations (addresses)
addresses
0
bk
...
1
...
2
...
0
b1 b0
...
n-1
columns
locations
...
Linear structure
1
2
.
.
c-1
0
1
Lines
2
location
.
bk
.
...
b1 b0
l-1
Matrix structure
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Characteristics of a memory circuit
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Geometry of internal organization:
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Memory capacity,
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The length of the memory word, organization and
addressing.
Expressed in number of memory locations or in bytes
For example:32 kbytes, 64 kB, 256MB, 1GB.
Volatility: loss of data
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ROM memory (Read Only Memories) – keeps/stores the
data even when the power supply is switched off
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ROM, PROM, EPROM, EEPROM, Flash
RAM memory (Random Access Memories): it looses its
content if the power supply is switched off
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Static RAM (SRAM)
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High speed, low capacity
Dynamic RAM (DRAM): it looses its memory in time
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Medium speed, very high capacity
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Characteristics of a memory circuit
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Memory technologies:
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Time features:
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bipolar (TTL, TTL Shottky, ECL) – fast but low
integration ratio, high power consumption
MOS, CMOS – high integration ratio, high capacity,
average speed, small power consumption
Access time: the time needed to read or write a
memory location; expressed in nanoseconds [ns].
The duration of a read or write cycle
The memory’s speed determined by its access time
or transfer cycle
Power consumption, expressed in w/bit.
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Bipolar memories have higher power consumption;
it depends on the capacity
MOS memories have very low power consumption;
it depends on the access frequency
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Non-volatile memories: ROM, PROM
EPROM, EEPROM, Flash
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The internal structure of a ROM memory
A0
A1
ADDR
ADDR
DEC
tCS
CS
tOE
OE
An
CS
PROG
OE
Valid Address
Control
logic
Valid Data
DATA
Data Amplifiers for read
and programming
tACC
tOH
TCYCLE
Dk
Dk-1
a.
D1
D0
b.
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Non-volatile memories: ROM, PROM
EPROM, EEPROM, Flash
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ROM
– Cannot be written, only read operations are allowed
Written by the producer (through masks)
PROM – Programmable ROM - One write (programming) operation
is allowed for the used
EPROM (UV) – Erasable PROM – a limited number of erase and
re-write operations are allowed (aprox. 100 cycles)
EEPROM – Electrically EPROM – electrical erase and re-write
(aprox. 100.000 cycles)
Flash – type of EEPROM with a block organization and higher
capacity
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T
WL
T1
F
T
PL

DL
ROM
WL
Vcc
WL
DL
PROM
T2
EPROM
DL
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Static RAM memories
TCITIRE
ADDR
A0
A1
ADDR
DEC
tCD
CS
Memory matrix
R/W “1”
DATA
An-1
Input
amplifier
CS
Valid address
Control
logic
k
Output
amplifier
tACC
b1.
TSCRIERE
k
ADDR
Input/output circuit
WR
Valid
Data
Valid address
CS
Dk-1
Dk-2
D1
D0
R/W
DATA
Internal structure
Valid Data
tDM
Time diagrams for read and
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write operations
Structure of RAM memory
ID
A0
A1
ID 1
k-1
ID 0
D Q
D Q
D Q
C
C
C
D Q
D Q
D Q
C
C
C
D Q
D Q
D Q
C
C
C
ADDR
DEC
An-1
CS
R/W
OD
k-1
OD
1
OD
0
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Dynamic RAM memory
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The elementary memory cell is a condenser
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It is charged (logical 1) or not (logical 0) at write operation;
The charge is lost in time (in aprox. 2 ms)
High capacity
Requires refresh operations
0
1
2
.
. 2n/2-1
0
RAS
Raw
address
reg
Raw
addr.
dec
WL/W
1
WL/R
2
.
n/2
.
2n/2-1
A0
A1
An/2-1
n/2
Column
address
reg
CAS
T2
T1
T3
MUX / DMUX
/ 1: 2n/2-1
2n/2-1:1
n/2
WE
C
DL
DRAM
OD
ID
Memory cell
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Read, write and refresh cycles for
DRAM memory
TREAD
ADDR
Raw addr
TWRITE
Column addr.
ADDR
RAS
RAS
CAS
CAS
WE
WE
Valid data
DATA
Raw addr
DATA
Read cycle
Column addr.
Valod data
Write cycle
Trefresh
ADDR
Raw addr
RAS
CAS
WE
Refresh cycle
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Design of a static RAM memory
module
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The structure of a memory module
Address
Amp.
Addresses
Metrix of
memory
circuites
Data Amp.
Selection
Data
Module Control circuit
selection
Commands
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Design parameters
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Memory capacity (KB, MB)
Internal organization (ex: 8, 16, 32 bits)
The bus:
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•
Address lines, data lines and commands
Time restrictions
Start address (the module’s place in the
addressing space of the processor)
Type of available memory circuits
Other functional requirements
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Design steps
1.
2.
3.
4.
5.
6.
Building of a memory sub-module with
the required data width
Build the memory matrix with the
required capacity, using the previously
built sub-modules
Design the decoder module
Design of address amplifiers
Design of data amplifiers
Design of the control circuit (if needed)
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Design example
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Capacity: 1Mbytes
Organization: 16 bits with access on 8
bits too
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The bus:
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ISA (24 address lines, 16 data lines,
MRDC, MWTC)
Start address: C0000H
Available circuits: 64Kbytes
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Building a sub-module with the required data width
A1
D0
64K
*8
A2
A16
D1
D7
WR\
CSLi\
64K
*8
D8
D9
D15
CSHi\
Submodule 64K*16= 128K*8
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Building the memory matrix with the
required capacity
A1-A16
WR\
CSL0\
64K
*16
D0-D15
CSH0\
CSL1\
64K
*16
CSH1\
…
CSL7\
CSH7\
64K
*16
512K*16=1M*8
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Design of the decoder unit
A17-A23
CS0\
DEC
DEC
CS1\
CS7\
MRDC\, MWTC\
SelMod\
BHE\ A0
A23
A22
A21
A17
A18
A19
74LS
138
CSL0\
CSH0\
A20
CSL7\
MRDC\
MWTC\
SelMod\
CSH7\
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Design of address and data amplifiers
SA0
SA1
SA7
SA8
SA9
SA15
74LS
244
74LS
244
A0
A1
A7
A8
A9
A15
SD0
SD1
SD7
RD\
SelMod\
SD8
SD9
SD15
SA16
SA23
74LS
244
74LS
245
74LS
245
D0
D1
D7
D8
D9
D15
A16
A23
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Design of a DRAM memory module
Address bus
Data bus
MUX
2:1
MUX
A
2:1
Amp
date
B
DRAM
Refresh
Counter
AdrSel
WR\
MRD\
MWR\
Command
device
CSM\
RAS\
W\
CAS\
CAS0\,CAS1\,….CASn\
RAS\
CAS\
Oscilator
RefReq
DEC.
...
CS0\, CS1\, ..CSn\
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