Transcript Slide 1

Structure of Computer
Systems
Course 8
Memory system
Memory – as main component of a
von Neumann computer

Role:


stores instruction codes and data
Basic types:

registers - contained in the CPU
• register types: general purpose registers, instruction register, program
counter, stack pointer, control and status registers
• access – direct through internal links or buses
• access time – 1 clock period or less

internal or main memory
•
•
•
•

access: through the system bus – read/write transfer cycles
random access to every location, based on the location’s address
technology: semiconductor circuits
access time: 1—70ns
external memory
•
•
•
•
indirectly accessible through interfaces and system bus
sequential or partially random access to blocks of memory (e.g. sectors)
technology: magnetic , optical, semiconductor
access time: 0.1-10ms
Memory system

New memory types:

Cache memory
• high-speed low capacity memory between the CPU and the
internal memory
• keeps copies of the main memory’s zones (lines)

Virtual memory
• extension of the internal memory on the external memory
• mechanisms for protecting memory zones allocated for
different purposes

Memory hierarchy =
• cache memory
• internal memory
• virtual memory
Memory technologies
(semiconductor technologies)
 Basic

classification:
ROM
• non-volatile memory
• types: ROM, PROM, EPROM, EEPROM, Flash

RAM
• volatile memory
• types:


Static RAM (SRAM):
• bipolar, CMOS
Dynamic RAM (DRAM)
• (basic) DRAM, FPM DRAM, EDRAM, SDRAM,
DDRAM1, 2, 3, RAMBUS-DRAM
Memory design issues

Access:

address-based:
• random – every location can be accessed randomly based on its address
(e.g. RAM, ROM)
• sequential – the locations are read or written one after the other (magnetic
tape, CCD – charge coupled devices)




partial random – random at block level (e.g. sector) and sequential inside a
memory block (e.g. magnetic and optical disk)
associative – a location is found based on a tag (content) associated to
every location
stack – a location is found on top of the stack – the stack pointer is
automatically incremented or decremented for read and write operations
Volatility:


non-volatile memories – does not lose their content when the power is
switched off (e.g. ROM, PROM, EEPROM, Flash)
volatile memories – lose their content without power supply
• static memories – preserve the data as long as the circuit has power supply
• dynamic memories – lose their content in time (e.g. DRAMs) even if power is
ON - requires periodic refresh cycles
Memory design issues

communication:

through a parallel bus – address, data and control signals
• asynchronous bus – classical bus controlled through control signals
(e.g. 8086 bus)
• synchronous bus – controlled through the clock signal (e.g. P6 bus)



through a serial bus – serial transmission based on a protocol
(e.g. SPI, I2C)
trough an interface – indirect access (e.g. hard-disc interface)
organization:


uniform access – every location accessed in the same way
non-uniform memory access (NUMA) – access depends on the
position of the memory relative to a given CPU
Memory system – basic concepts

memory cell




smallest storing unit
preserves 1 logical variable – 1 bit (binary digit)
usually, not directly accessible
implementations:
•
•
•
•
•

flip-flop (2,4, 6 transistors) - SRAM
a condenser (1 CMOS transistor) – DRAM
conductor/isolator – ROM, PROM, EPROM EEPROM
magnetic polarization – magnetic disc
transparent/opaque surface – optical disc
memory location



a group of memory cells (8, 16, 32 bits) addressable as an individual
addressing: unique address, incremental or sequential, associative
a memory location has:
• an address and
• a content
Memory system – basic concepts
 Examples
of memory cells
T
sel
sel
Vcc
sel
T1
F
T
PL

D
D
T2
PROM
ROM
D
EPROM
D
sel/W
sel/R
SRAM
T1
T2
T3
seli
DRAM
C
D
D
Memory system – basic concepts

memory structure (block)

linear organization – locations placed one after the
other at ascending addresses
....
Address
0
1
2
Dm Dm-1 Dm-2

3
4
...
D0
5
..FFD ..FFE
..FFF
one location
matrix organization – a location is at the intersection of a line
Columns
and a column
1
Lines
2
0
1
2
3
1
..FF
3
4
..FF
....
....
....
....
....
....
Dm Dm-1 Dm-2
...
one location
D0
Memory system – basic concepts

Memory structure

internal structure of a ROM or SRAM memory circuit
Address A0-An
DEC
Sel0
Sel1
...
Chip select CS
Write signal Wr
Control unit
Components
•
•
•
•
Memory
locations
Sel
or program

Data
Amp
address decoder
memory locations
data amplifier
control unit
Dir
OE
Data D0-Dm
Memory system – basic concepts

Time diagrams for memory read and memory write cycles
Read Memory Cycle
A0-An
valid address
CS
Wr
D0-Dm
valid data
taccess
tcycle
Write Memory Cycle
A0-An
valid address
CS
Wr
D0-Dm
valid data
taccess
tcycle
Memory system – basic concepts

Memory structure

internal structure of a DRAM memory circuit
Column
RAW addr
RAW
addr
buf
RAW
DEC
Col
addr
buf
Column addr
RAW
Address
RAS
CAS
DATA MUX
Control
unit
Din
Dout
Memory system – basic concepts

DRAM memory:

Components:
•
•
•
•
•

raw and column address buffers
raw address decoder
column data multiplexer
memory locations
control unit
Issues
• too many address lines
• memory must be refreshed raw by raw

Solutions:
• address lines are multiplexed in time (half of the address pins
are needed)
• two extra selection signals:


RAS – Raw address select
CAS – Column address select
• no chip select line
• external refresh cycles
Memory system – basic concepts

Time diagram for DRAM memory read cycle
Memory Read Cycle
A0-An/2
Raw
Column
RAS
CAS
Wr
D0-Dm
valid data
taccess
tcycle
Memory system – basic concepts

Time diagram for DRAM memory write cycle
Memory Write Cycle
A0-An/2
Raw
Column
RAS
CAS
Wr
D0-Dm
valid data
taccess
tcycle
Memory system – basic concepts

Time diagram for DRAM memory refresh cycle
Memory Refresh Cycle
A0-An/2
Raw
RAS
CAS
Wr
D0-Dm
tcycle
Memory system – basic concepts

Access time





one of the most important parameter of a memory
circuit
measures the time required to perform a read or write
operation
measured from the moment when address lines are
stable until the data is read or written in the memory
smaller access time => higher speed
taccess = taddr_dec + tcell_read/write + ten_amp
depends on capacity
constant for a technology
enable/disable time
Memory system – basic concepts

Access time (cont)

depends on technology
• ROM – medium – 20-30 ns
• SRAM – small – 10-15ns
• DRAM – high – 70ns (basic DRAM); 10-15ns (DDRAM – block
read)

Read/write cycle period



minimum time needed to perform a complete read or a write
operation
measured from the moment address signals are stable until the
address and data lines may be disabled
Technology dependences:
• constant time for SRAM, ROM; variable for DRAM (see refresh)
• same for read and write – SRAM, DRAM; write is much longer –
Flash, EEPROM
Memory system – basic concepts
 Memory



capacity
number of locations or bytes
measured in kilo (k), mega (M), giga (G) or
terra (T) locations or bytes
capacity is dependent of technology
• ROM, SRAM technologies:


small capacity/chip – 64KB-4MB
flash – 4-64GB
• DRAM technologies:

high capacity/chip – 2-8 GB
New DRAM technologies

Why DRAM memories?



Problems with DRAMs:
require periodic refresh cycles
 address multiplexing
 too long access time (70ns)
Conclusions:
 most of today’s computers use DRAM circuits as their
main memory
 we have to do something to reduce the access time
and to reduce the impact of extra refresh cycles


very big capacity/chip (1-4GB) at a reasonable price
SRAMs cannot be implemented at such capacities
New DRAM technologies
 FPM-DRAM

idea – one raw address and multiple column
addresses – sequential block read/write:
• data1,2,4 – read; data3 – write
A0-An/2
Raw
Col1
Col2
Col3
Col4
RAS
CAS
Wr
D0-Dm
data1
taccess
taccess
data2
taccess
data3
taccess
data4
No delay for
EDO-DRAM
New DRAM technologies

EDO-DRAM – Enable Data Output DRAM


an extra output enable signal (OE) that eliminate the
delay between two consecutive columns (see
previous diagram)
BEDO-DRAM Burst EDO-DRAM

consecutive column addresses are generated inside
the memory chip (no extra CAS cycles are needed)
DRAM
FPM DRAM
EDO
DRAM
BEDO
DRAM
SDRAM
First access time (ns)
70
50
50
52
50
Cycle time (ns)
100
30
20
15
10
5
16-66
33-75
60-100
60-100+
Time parameter
Bus speed (MHz)
New DRAM technologies

SDRAM – synchronous DRAM






synchronous mode; every signal controlled by the
processor’s clock signal
memory organized on blocks that can work in parallel
promotes burst data transfers (1,2,4, 8 or a whole page)
pipelined access to the memory; a new access may be
initiated before the previous ended
consecutive addresses generated inside the memory chip
access time is 4 times smaller than classic DRAM
New DRAM technologies
 SDRAM
– synchronous DRAM (cont.)
Clock
Command Read
Nop
Nop
Nop
Read
Nop
Nop
Address
Data
Dn
Dn+1
Dn+2
taccess
Block n
Block m
Dn+3
Dm
New DRAM technologies

DDR – SDRAM – Double Data Rate SDRAM



makes data transfer on both edges of the clock signal (double
pumping) – reduces the required clock frequency to half
very strict timing conditions
64 bit transfers
DDR SDRAM
Bus clock
(MHz)
Internal Bus
clock (MHz)
Prefetch
(min burst)
Transfer Rate
(MT/s)
Voltage
DDR
100-200
100-200
2n
200-400
2.5
DDR2
200-533
100-266
4n
400-1066
1.8
DDR3
400-1066
100-266
8n
800-2133
1.5
Design of memory modules

Design parameters:

capacity:
• in number of locations or bytes

organization:
• bits/location
• addressing: random, sequential addressing (FIFO, LIFO),
associative

bus specifications:
• address and data signs
• control signals
• timing (time diagrams)

starting address:
• place of the designed module in the addressing space of the
processor


available circuits
special requirements (e.g. refresh, periodic access, etc.)
Design of ROM or SRAM memory
modules

Steps:
1. build a sub-module with the required data
width
2. build the memory matrix
3. design the address decoder
4. address amplifiers
5. data amplifiers
6. control unit (if necessary)
Design of a SRAM memory modules
Design parameters:



Capacity: 1Mbytes
Organization: 16 bits with access on 8 bits too
The bus:
• ISA (24 address lines, 16 data lines, MRDC, MWTC)

Start address: C0000H
Available circuits: 64Kbytes
Sel
Addresses sig
Metrix of
memory
circuites
Module
selection
Command sig.
Control circuit
Data
Amp.

Address
Amp.

Data
Building a sub-module with the required data
width
A1
D0
64K
*8
A2
A16
D1
D7
WR\
CSLi\
64K
*8
D8
D9
D15
CSHi\
Submodule 64K*16= 128K*8
Building the memory matrix with
the required capacity
A1-A16
WR\
CSL0\
64K
*16
D0-D15
CSH0\
CSL1\
64K
*16
CSH1\
…
CSL7\
CSH7\
64K
*16
512K*16=1M*8
Design of the decoder unit
A17-A23
CS0\
DEC
DEC
CS1\
CS7\
MRDC\, MWTC\
SelMod\
BHE\ A0
A23
A22
A21
A17
A18
A19
74LS
138
CSL0\
CSH0\
A20
CSL7\
MRDC\
MWTC\
SelMod\
CSH7\
Design of address and data amplifiers
SA0
SA1
SA7
SA8
SA9
SA15
74LS
244
74LS
244
A0
A1
A7
A8
A9
A15
SD0
SD1
SD7
RD\
SelMod\
SD8
SD9
SD15
SA16
SA23
74LS
244
A16
A23
74LS
245
74LS
245
D0
D1
D7
D8
D9
D15
Design of a DRAM memory module
Address bus
Data bus
MUX
MUX
2:1
Amp
2:1
DRAM
Refresh
Counter
RAS
W
CAS
AdrSel
WR \
MRD \
MWR \
Command
device
CSM \
CAS0 \,CAS1 \,….CASn
RAS \
CAS \
Oscilator
RefReq
DEC.
CS0 \, CS1 \, ..CSn