Transcript EMC guidelines for Automotive ICs

http://www.ic-emc.org
EMC Guidelines for Automotive
Integrated Circuits
Etienne SICARD
Professor, INSA Toulouse, FRANCE
[email protected]
May 2006
7/17/2015
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Summary
1. Context
3. Consequence on EMC
3. Design issues
4. Measurement methods for ICs
5. Design guidelines
6. Conclusion
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1. Context
Susceptibility
Emission
System
Personal entrainments
Mobile
phone
Boards
Safety
systems
Component
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1. Context
250
250nm
220nm
Technology Node (nm)
220
2X reduction
Interconnect
delay
Copper
130
25% Performance Boost
Nickel Silicide & Strained Silicon
180nm
180
90
20% Faster @ Same Power
PD SOI
50% reduction in static power
Metal Oxide & Gate Dielectric
130nm
10% Reduction
in Dynamic Power
Low K1 ILD
90nm
65nm
10% Reduction
in Dynamic Power
Low K2 ILD
1
65
2X Density Increase per Node
Metal Gate
30% Scaling per Node
Wet 193nm
Superior LP & RF
FDSOI
45nm
45
Metallization
Innovations
30
32nm
Up to 4X fewer devices/function
MIGFET
Transistor
Innovations
<20
98
99
00
© Freescale semiconductors
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02
03
04
05
06
07
08
09
<10- 20nm
10
11
12+
Year
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1. Context
IC tech.
0.18µm
0.12µm
50M
100M
1999
2001
90nm
65nm
45nm
Complexity
250M
500M
1G
Packaging
µC
16 bit
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µC
32 bit
2003
µC+DSP
Flash
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2µC+4DSP
Flash,
eRam
2007
Multicore, DSP
FPGA, eRam
RF multiband
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2. Consequence on EMC
Ampere
Evaluation of the current in ICs
1.0
0.1- 1.0 mA per gate
1-100 Million gate per IC
Current peak at each clock edge
1ns
10%-30% switching activity
Current peak spread due to non-synchronous switching
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time
16-bit micro : 1A
32-bit micro : 10A
64-bit micro : 100A
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2. Consequence on EMC
More I/Os, less noise margin
Supply (V)
5.0
I/O supply
3.3
2.5
Core supply
1.5
0.7
0.5µ
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0.35µ
0.18µ
90nm
65nm Technology(m)
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3. Design Issues
EMC problems handled at the end of design cycle : 3rd cause of redesign
DESIGN
FABRICATION
Architectural
Design
Design Entry
Design Architect
Version n°
Version n°
EMC Measurements
Compliance ?
NO GO
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GO
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3. Design Issues
EMC validated before fabrication
DESIGN
Architectural
Design
Tools
Design Guidelines
Training
Design Entry
Design Architect
EMC Simulations
Compliance ?
NO GO
GO
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FABRICATION
EMC compliant
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4. Measurement methods
Mature international standards for emission measurement IEC 61967
Radiated
DC-1GHz
SAE J1752/3
IEC 61967-2
TEM Cell
Radiated
DC-18GHz
Conducted
DC-1GHz
GTEM Cell
VDE 1
1997
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IEC 61967-4
UK 767.14
1999
2001
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2005
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4. Measurement methods
International standard for emission measurement IEC 62132
Conducted
DC-400MHz
Bulk Current injection
Conducted
DC-1GHz
IEC 62132-2
IEC 62132-3
Direct power injection
Conducted
DC-1GHz
Workbench Faraday Cage
1997
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2001
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IEC 62132-5
2003
2005
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5. Design Guidelines
Reduce supply inductance
Why: because inductance is a major source of resonance
IC
Avoid power lines on long leads
Rule of thumb: 2 supply for
8 I/Os, close to core
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5. Design Guidelines
Place supply/ground as close as possible
Why:
• to reduce current loops that provoke magnetic field
• to increase decoupling capacitance
Added contributions
Canceled contributions
EM wave
-20dB
current
Lead
Lead
Die
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5. Design Guidelines
Place supply/ground as close as possible – case studies
Case study 1
supply
Case study 2
ground
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5. Design Guidelines
Add on-chip capacitance
Parasitic emission
(dBµV)
Customer’s
specification
80
Why:
• to keep the current
flow internal
• to reduce the supply
voltage swing
70
60
50
No decoupling
40
30
20
1nF 10
decoupling
0
-10
1
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f (MHz)
100
1000
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5. Design Guidelines
Add on-chip capacitance – case study
• 1nF added to a
“normal” 16-bit core
• More than 15dB
noise reduction
Normal
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On-chip decoupling
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5. Design Guidelines
Add on-chip capacitance
– case study
Metal-Insulator-Metal
capa over FLASH
memory
Junction capacitance
underneath buses
« filler
capacitance »
close to IOs
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5. Design Guidelines
Noise isolation inside IC blocks
Bulk isolation
Why:
• to reduce the injected noise
and the auto-susceptibility
How
• by locating fast signals with
strong currents
• by separate voltage supply
• by substrate isolation
Noisy
blocks
Standard
cells
Analog
Far from
noisy blocks
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Separate supply
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5. Design Guidelines
Reduced drive whenever possible
30
8mA I/O
4mA I/O
25
20
3-4 dB
dBuV
15
10 dB
10
5
0
-5
1
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10
f (MHz)
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100
1000
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5. Design Guidelines
Overall reduction of parasitic emission: up to 40dB !
Emission level
(dBµV)
Spectrum envelope of the
original application IC
50
40
Application IC with
low-emission design
guidelines
30
20
10
0
0.1
1
10
100
1000
Frequency (MHz)
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5. Design Guidelines
Defensive software in microcontrollers
ADC
Why:
• Helps the micro to handle
interference
How
• by redundancy, error coding
• by watch-dogs
• by memory refresh
• by input data checking
• by filling unused memory
with “Go to Error”
Injection
Power (dBm)
DUT
Test board
20
15
10dBm limit
Defensive
software
10
5
Normal
software
0
-5
1
10
100
1000
10000
Frequency (MHz)
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5. Design Guidelines
Improved immunity thanks to on-chip
capacitance
With 1nF onchip
Power (dBm) required to generate a failure
50
40
30
20
Witout on-chip
decoupling
10
0
100
200
300
400
Frequency (MHz)
500
1000
Direct power injection on IC supply of CESAME
test-chip by R. Perdriau ESEO, France
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5. Design Guidelines
Rising EMC expertise in IC design companies
Peak noise (dBµV)
90
70
32bit
16bit
8bit
Emission
reduction
techniques
50
• EMC measurement
methods
• Emission reduction
techniques
• Emission models
• Emission prediction tools
30
10
1996
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1999
2002
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6. Conclusion
•
Trend towards higher complexity and frequencies
•
EMC investigated late in the design flow
•
Mature standard measurement methods dedicated to ICs
•
Golden rules for EM compatibility exist
•
Proven efficiency for low emission
•
Knowledge and customer support in EMC is a commercial argument
•
Soon, requirements up to 10GHz, new design rules to be settled
•
Pressure to handle electromagnetic reliability of ICs
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Learn more…
Tools
www.springeronline.com
www.ic-emc.org
Workshops
www.emccompo.org
Standards
•IEC 61967, 2001, Integrated Circuits emissions
•IEC 62132, 2003, integrated circuits immunity
•IEC 62014-3, 2003, Integrated Circuit Model
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