Transcript Origin of Parasitic Emission

Electromagnetic compatibility of
Integrated Circuits
INSA Toulouse - France
October 2012
Alexandre BOYER
INSA/DGEI
University of Toulouse
31077 Toulouse - France
[email protected]
Etienne SICARD
INSA/DGEI
University of Toulouse
31077 Toulouse - France
[email protected]
www.alexandre-boyer.fr > Enseignement
www.ic-emc.org
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Objectives
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Through lectures (16 H)
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Understand parasitic emission mechanisms
Introduce parasitic emission reduction strategies
Give an overview of emission and susceptibility measurement
standards
Power Decoupling Network modelling
Basis of conducted and radiated emission modelling
Basis of immunity modelling
Understand the role of decoupling at printed-circuit-board level
Acquire basic knowledge of design for improved EMC at PCB and IC
level
Illustrate basic concepts through simulation (10 H)
IC modeling case study using DSPIC (10 H)
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EMC of ICs
An overview
Outlines
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Electromagnetic interference
 What is EMC
 EMC at IC level
 Origin of parasitic emission
 Trends towards higher emission
 Origin on susceptibility
 Emission issues
 Susceptibility issues
 Standardization issues
 Conclusion
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Electromagnetic Interference
EMI ISSUES IN WIRELESS DEVICES
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Numerous interference cases reported over the ISM band 2400 – 2483.5 MHz.
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From Cisco, « 20 Myths of WiFi Interference », White Paper, 2008:
•
“Interference contributes to 50 % of the problems on the customer’s Wi-Fi network. “
•
“In a recent survey of 300 of their customers, a major Wi-Fi tools provider reported that
“troubleshooting interference won ‘top honors’ as the biggest challenge in managing a
Wi-Fi network.””
•
“67 percent of all residential Wi-Fi problems are linked to interfering devices, such as
cordless phones, baby monitors, and microwave ovens.”
•
“At 8m, a microwave oven degrades data throughput by 64%.”
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What is EMC ?
DEFINITION
« The ability of a component, equipment or system to operate satisfyingly in a
given electromagnetic environment, without introducing any harmful
electromagnetic disturbances to all systems placed in this environment. »
 Essential constraint to ensure functional safety of electronic or electrical
applications
 Guarantee the simultaneous operation of every electrical or electronic
equipment in a given electromagnetic environment
 Reduce both the parasitic electromagnetic emission and the sensitivity or
susceptibility to electromagnetic interferences.
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EMC at IC Level
ZOOM AT DEVICES
10 mm
100 mm
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Integrated
Circuits…
10µm
1mm
1V
100 µA
100 nm
1 µm
© Intel Xeon
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EMC at IC Level
WHY EMC OF IC ?
• Until mid 90’s, IC designers had no
consideration about EMC problems in
their design..
• Starting 1996, automotive customers
started to select ICs on EMC criteria
• Starting 2005, mobile industry required
EMC in System in package
• Massive 3D integration will require
careful EMC design
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EMC at IC Level
INCREASED INTEGRATED CIRCUIT COMPLEXITY
Technology
130nm
90nm
100M
250M
2004
2006
Core+
DSP
Core
DSPs
1 Mb
Mem
10 Mb
Mem
32nm
22nm
5nm
500M
2G
7G
150 G
2008
2010
45nm
Complexity
Packaging
Embedded
blocks
Dual core
Dual DSP
RF
Graphic
Process.
100 Mb Mem
Sensors
2012
Quad Core
Quad DSP
3D Image Proc
Crypto processor
Reconf FPGA,
Multi RF
1 Gb Memories
Multi-sensors
2020
?
EMC at IC Level
TWO MAIN CONCEPTS
Susceptibility to EM waves
Carbon airplane
Emission of EM waves
Personnal entrainments
Equipements
interferences
Boards
Radar
Safety systems
Components
Hardware fault
Software failure
Function Loss
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EMC at IC Level
THE ROLE OF ICS AS PERTURBATION SOURCE AND VICTIM
Integrated circuits are the origin of parasitic emission and susceptibility to RF
disturbances in electronic systems
Emission
Chip
Components
PCB
System
Radiation
Noisy
IC
Interferences
Sensitive
IC
Chip
Coupling
Components
PCB
Susceptibility
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System
Origin of Parasitic Emission
BASIC MECHANISMS FOR CURRENT SWITCHING
VDD
Switching current
IDD
Vin
Voltage
Output
capa
VSS
ISS
Time
Time
CMOS inverter exemple
Question: waveform, amplitude?
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Origin of Parasitic Emission
CMOS INVERTER IN IC-EMC
Waveforms strongly depend on load
Switching current
Voltage
Time
Time
Basic > interconnects > GateSwitching.sch
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Origin of Parasitic Emission
STRONGER SWITCHING CURRENT:
i(t)
Vdd
i(t)
i(t)
50ps
Vss
Switching gates

Time
Internal
switching current
Very large
Simultaneous
Switching Current
Main transient current sources:
 Clock-driven blocks, synchronized logic
 Memory read/write/refresh
 I/O switching
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Time
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Origin of Parasitic Emission
EXAMPLE: EVALUATION OF DSPIC SWITCHING CURRENT
• ____ VDD, ___ technology
• ____ mA / gate in ____ ps
• ____ gates in ____ Bit Micro => ____ A
• ____ % switching activity => ____ A
• ____ % current peak spread (non synchronous switching)
•____ in ____ ps
Current (A)
Current / gate
Current (A)
Vdd
i(t)
____
Vss
Current / Ic
____
time
____ ns
____ ns
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time
Origin of Parasitic Emission
REFERENCES: CURRENT, DECAP VS TECHNOLOGY
M. Ramdain, E. Sicard, “The Electromagnetic Compatibility of
Integrated Circuits—Past, Present, and Future”, IEEE Trans.
EMC, VOL. 51, NO. 1, Feb. 2009
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Origin of Parasitic Emission
Wires act as antennas
V(t)
Vdd
Vss
Time
L  _ nH / mm
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V  _
Origin of Parasitic Emission
WIRES+CURRENT = NOISE
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DSPIC33F noise measurement with active probe on X10
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Activation of the core by a 40 MHz internal PLL
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Synchronous ADDR0..15 bus switching 0x0000, 0xFFFF
DSPIC_VDD_VofT.tran
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Origin of Parasitic Emission
WIRES RADIATE
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Emission Issues
WHY TECHNOLOGY SCALE DOWN MAKES THINGS WORSE ?
• Current level keeps
almost constant but:
• Faster current
switching
Volt
Old process
New process
Time
Current
Stronger di/dt
di/dt
Old process
New process
Time
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Increase parasitic noise
Susceptibility issues
DECREASED NOISE MARGIN IN ICS
Supply (V)
500 mV
100 mV
margin
margin
5.0
3.3
I/O supply
2.5
Core supply
1.8
1.2
1.0
0.5µ
0.35µ
0.18µ
130n
90n
65n
Technology
45n
32n
22n
Adapted from ITRS roadmap for semiconductors, 2011
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17n
Susceptibility Issues
UNINTENTIONAL ELECTROMAGNETIC SOURCES
Power
HF
VHF
UHF
SHF
xHF
THF
Weather Radar
1GW
Radars
• Fields
radiated
by
electronic
devices
1MW
Thunderstorm impact
TV UHF
1KW
TV VHF
2-4G BS
1W
4G 2G 3G
1mW
3 MHz
25m
30 MHz
2.5m
300 MHz
3 GHz
0.25m
25mm
30 GHz
2.5mm
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300 GHz
0.25mm
• Continuou
s waves &
pulsed
Frequency
waves
/4 (ideal antenna)
Susceptibility Issues
SYSTEM-ON-CHIP, 3D STACKING: DANGER
EMC Level
(dB)
50
Susceptibility
level
40
30
20
10
0
High risk of
interference
Safe
interference
margin
Unsafe margin
-10
-20
-30
-40
1
Sum of
perturbations
10
100
1000
Frequency (MHz)
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Conclusion
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EMI reported in all kinds of devices
IC involved in many EMI problems
IC technology evolution towards
higher complexity
On-chip switching currents in the
10-100 A range
ICs are good antennas in the GHz
range
Increased switching noise
Increased emission issues
Reduced noise margins
System-on-chips, systems-inpackage rise new EMC issues
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