Transcript Digital Decode & Correction Logic

Digital Decode & Correction
Logic
Preliminary design review
PAYAL DAVE
Outline
• Introduction
• Why Digital Decode & Error correction
logic requires
• Main Block diagram
• Individual block explanation
• Sims result
• Conclusion
A7
D7
B7
A6
D6
B6
A5
D5
B5
Need for Digital Decode & Error
Correction
• To eliminate the redundancy of ½ bit in each stage
• Digital correction takes raw output data of the ADC as
input and outputs the digital representation.
• Error correction logic circuitry takes 14 bit input from
ADC stages and eliminated the redundancy of ½ bit in
each stage and gives 8 bit digital output.
• Digital circuits are fast and take low power.
How it is done?
• Requirements:




Align ADC (comparator) decisions
Correct ADC output bit pattern
Add digital data in a 1.5-bit fashion
Output a 8-bit digital word
• Implementation:
 Shift register using Delayed D flip flop
 Ripple carry adder
Main Block Diagram
A7 B7 A6 B6 A5 B5
A4 B4
A3 B3 A2 B2
A1 B1
CLK1
CLK2
SHIFT REGISTER
Ripple Carry Adder
CLK2
Output register
D7
D6
D5
D4
D3
D2
D1 D0
Shift register to align ADC
decisions
STG -1
CLK1
DFF
CLK2
DFF
STG -2
STG -4
STG -6
Shift register
using D flipflop
DFF
DFF
DFF
DFF
DFF
DFF
DFF
DFF
DFF
DFF
DFF
DFF
CLK1
CLK2
STG -7
DFF
CLK1
CLK2
STG -5
DFF
CLK1
CLK2
STG -3
DFF
DFF
DFF
DFF
DFF
RIPPLE CARRY ADDER
DFF
DFF
SHIFT REGISTER TEST BENCH
SHIFT REG
ALIGNING OF 14 BITS WITHIN 31/2 CLK
Digital correction logic
A7
A6
B6
A5
STAGE - 3
B5
B4
A4
Concept of
Digital
Correction
+
STAGE - 1
STAGE - 2
B7
A3
STAGE -4
B3
A2
D7
D6
D5
D4
D3
*
Z = D
Y = B XOR C
X = A + BC (CARRY BIT)
*
D2
STAGE - 5
STAGE -6
B2
A1
B1
D1
STAGE 7
D0
*
A
B
C
D
Y
Z
+
Mathematical analysis
Of Digital Correction
X
Logic Equations used for RCA
• Total gate delay for RCA
C0 = A2 + A1B2
C1 = B3C0 + A3
C2 = B4C1 + A4
C3 = B5C2 + A5
C4 = B6C3 + A6
D0 = B1
D1 = A1 XOR B2
D2 = C0 XOR B3
D3 = C1 XOR B4
D4 = C2 XOR B5
D5 = C3 XOR B6
D6 = C4 XOR B7
D7 = B7C4 + A7
RIPPLE CARRY ADDER
CARRY BIT
A + BC
SS With worst case for 4.5v & 85C
The delay in SS with worst case is
6.34ns
SIMS RESULTS FOR DIFFERENT
CORNERS FOR RCA
5.5 v
0
27
5.0v
85
0
27
4.5v
85
0
TT
SS
FS
FF
SF
4.26n
4.63n
5.44n
4.94n
3.70n
2.69n
27
85
3.97n
4.65n
5.38n 6.34n
4.02n 4.73n
2.89n
3.36n
3.92n
4.60n
ALIGNING OF 14 BITS WITHIN 31/2 CLK
Error Correction Logic
A7B7 A6B6 A5B5 A6B6 A4B4 A3B3 A2B2 A1B1
01 01 01 01 01 01 01
D7 D6 D5 D4 D3 D2 D1 D0
01 1 1 1 1 1 1 1 1
01 01 01 01 01 01 01 10
000000 00
11 11 11 11 11 11 11 11
00000001
10 10 10 10 10 10 10 10
01111110
10 10 10 10 10 10 10 01
01111101
SHIFT REGISTER WITH RCA AND OUTPUT REGISTER
SHIFT REGISTER
RCA WITH OUTPUT REG
30n
35n
Pulse width linear input to shift reg
Conclusion
• 14 bits coming from the comparator are
aligning with the help of the shift register
within 41/2 clock cycle.
• Ripple carry adder takes 6.34ns for worst
case condition which is fast enough to get
desired output
• Error correction logic is working for
different combination of input bits.