Transcript INO TRIDAS activities at Mumbai

Design of electronics, trigger and data
acquisition system for the proposed INO
prototype detector
B.Satyanarayana
(For INO collaboration)
Department of High Energy Physics
Tata Institute of Fundamental Research
Homi Bhabha Road, Colaba, Mumbai, 400 005
E-mail: [email protected]
INO prototype detector
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Detector and signal specifications
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Trigger information
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Expected trigger rate is few Hz
Required Trigger logic is m X n fold, where
m = 1 to 4; no. of consecutive channels in a layer
n = 5 to 1; no. of consecutive layers with m fold in each layer
ie m x n = (1 x 5) OR (2 x 4) OR (3 x 3) OR (4 x 2)
Information to be recorded on a trigger
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Detector dimensions: 1m X 1m X 1m
14 layers of RPCs with 6cm iron plates interleaved.
Two signal planes orthogonal to each other and each having 32 pick-up strips
Total channels = 32 X 14 X 2 = 896
Pulse height = 100 to 300mV; Rise time = < 1 ns
Pulse width = ~50ns; Rate ~ 1KHz
Absolute arrival time of the trigger
Track identification (XYZ points in RPC layers)
Direction of track ( TDC information)
Miscellaneous information and calibration data
Monitoring health of the detector
XVI DAE-BRNS Symposium on HEP
SINP, Kolkata
Nov 29 - Dec 3, 2004
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Readout scheme for prototype
X-plane
Y-plane
Front End
Electronics
Y
X
1
CAMAC
RTC
Final
Trigger
TDC
2
1
Event Scalers
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FEE
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9
Control Logic
Read Data &
Monitor
Monitor
Scalers
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10
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14
CAMAC
Controller
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Trig & TDC
Router
LAN
XVI DAE-BRNS Symposium on HEP
SINP, Kolkata
PC
(LINUX)
Nov 29 - Dec 3, 2004
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32-channel front-end module
1 2 3 ……………………………………………………………32
Trigger 0
Logic (ECL)
&
Trigger 1
M fold Logic
( CPLD )
LVDS
32 ECL Comparators
Threshold
Timing signal
Level Translator & Wave shaper (32+8)
Mon SI
EVE (SW4)
Board ID (SW8)
Monitor
MUX unit
( 40 : 1 )
MON(SW4)
Mon SO
Addr & Control
Module
Selection
Counter
Event Trig
SHIFT REGISTER ( 48 bit )
Eve SI
Eve SO
FPGA
XVI DAE-BRNS Symposium on HEP
SINP, Kolkata
Nov 29 - Dec 3, 2004
4
Prototype detector trigger logic
Front End Electronics
Level-0
X-Plane
Y-Plane
S1=1+9+17+25
S2=2+10+18+26
……….
S8=8+16+24+32
S1….S8
Level 1
S1…S8
L14P1
(mF)
L1P1
(mF)
S1…S8
L14P2
(mF)
L1P2
(mF)
1F,2F……4F
1F,2F……4F
(LVDS interface)
1F,2F……4F
Trigger & TDC signals
Router
1F,2F……4F
Trigger & TDC signals
Router
Level-2 ( Back end )
F1(14)…………..F4(14)
F1(14)…………..F4(14)
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P1
(m x n fold)
P2
(m x n fold)
OR
Final Trigger
XVI DAE-BRNS Symposium on HEP
SINP, Kolkata
Nov 29 - Dec 3, 2004
5
Readout scheme for final detector
The keywords are channel count and fast timing
XVI DAE-BRNS Symposium on HEP
SINP, Kolkata
Nov 29 - Dec 3, 2004
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