Transcript INO TRIDAS activities at Mumbai

Status report on electronics, trigger and
data acquisition system for the proposed
INO prototype detector
B.Satyanarayana
Department of High Energy Physics
Tata Institute of Fundamental Research
Homi Bhabha Road, Colaba, Mumbai, 400 005
E-mail: [email protected]
INO prototype detector
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Detector and signal specifications
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Trigger information
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Expected trigger rate is few Hz
Required Trigger logic is m X n fold, where
m = 1 to 4; no. of consecutive channels in a layer
n = 5 to 1; no. of consecutive layers with m fold in each layer
ie m x n = (1 x 5) OR (2 x 4) OR (3 x 3) OR (4 x 2)
Information to be recorded on a trigger
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Detector dimensions: 1m X 1m X 1m
14 layers of RPCs with 6cm iron plates interleaved.
Two signal planes orthogonal to each other and each having 32 pick-up strips
Total channels = 32 X 14 X 2 = 896
Pulse height = 100 to 300mV; Rise time = < 1 ns
Pulse width = ~50ns; Rate ~ 1KHz
Absolute arrival time of the trigger
Track identification (XYZ points in RPC layers)
Direction of track ( TDC information)
Miscellaneous information and calibration data
Monitoring health of the detector
B.Satyanarayana
VECC, Kolkata
December 24, 2005
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Readout scheme for prototype
X-plane
Y-plane
Front End
Electronics
Y
X
1
CAMAC
RTC
Final
Trigger
TDC
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1
Event Scalers
2
FEE
8
9
Control Logic
Read Data &
Monitor
Monitor
Scalers
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10
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14
CAMAC
Controller
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Trig & TDC
Router
LAN
B.Satyanarayana
VECC, Kolkata
PC
(LINUX)
December 24, 2005
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Fast preamplifier
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Provided by Electronic Division, BARC
Currently being used with avalanche mode
operation
Fixed gain (10), single channel, single polarity,
with discrete components (availability issues)
B.Satyanarayana
VECC, Kolkata
December 24, 2005
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Preamp hybrid
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Bipolar operation tested
To be packaged into a hybrid (BEL)
Possible to mount on the RPC pickup strips
Will improve signal to noise
Fabrication procedure
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Circuit schematic by BARC
Layout preparation by BEL (2-3 weeks)
Pilot production by BEL and validation (1 month)
Final production (4-6 weeks)
B.Satyanarayana
VECC, Kolkata
December 24, 2005
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16-channel analog front-end
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Based on Analog Devices’ Quad-device
Fast comparator with ECL outputs
Wire ORed pre-trigger outputs
Production board tested with RPC strip signals
Works as good as commercial units
Components being procured
Ready for production (2-3 months)
B.Satyanarayana
VECC, Kolkata
December 24, 2005
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32-channel digital front-end
1 2 3 ……………………………………………………………32
Trigger 0
Logic (ECL)
&
Trigger 1
M fold Logic
( CPLD )
LVDS
32 ECL Comparators
Threshold
Timing signal
Level Translator & Wave shaper (32+8)
Mon SI
EVE (SW4)
Board ID (SW8)
Monitor
MUX unit
( 40 : 1 )
MON(SW4)
Mon SO
Addr & Control
Module
Selection
Counter
Event Trig
SHIFT REGISTER ( 48 bit )
Eve SI
Eve SO
FPGA
B.Satyanarayana
VECC, Kolkata
December 24, 2005
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Digital front-end status
• Logic fused into a CPLD XC 95288 -HQ708
• Code tested on a simulator and hardware using a
pattern generator
• Jig fabricated to test the logic on RPC signals
• Work in progress (2 weeks)
• PCB layout is also in progress
• Production estimate about 3 months
B.Satyanarayana
VECC, Kolkata
December 24, 2005
8
Prototype detector trigger logic
Front End Electronics
Level-0
X-Plane
Y-Plane
S1=1+9+17+25
S2=2+10+18+26
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S8=8+16+24+32
S1….S8
Level 1
S1…S8
L14P1
(mF)
L1P1
(mF)
S1…S8
L14P2
(mF)
L1P2
(mF)
1F,2F……4F
1F,2F……4F
(LVDS interface)
1F,2F……4F
Trigger & TDC signals
Router
1F,2F……4F
Trigger & TDC signals
Router
Level-2 ( Back end )
F1(14)…………..F4(14)
F1(14)…………..F4(14)
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P1
(m x n fold)
P2
(m x n fold)
OR
Final Trigger
B.Satyanarayana
VECC, Kolkata
December 24, 2005
9
CAMAC based trigger module
m-Fold LVDS
signals (X-Plane)
FR
C
60
FR
C
60
5 Fold coincidence
of consecutive F1
signals from 1 to
14 layers
4 Fold coincidence
of consecutive F2
signals from 1 to
14 layers
3 Fold coincidence
of consecutive F3
signals from 1 to
14 layers
2 Fold coincidence
of consecutive F4
signals from 1 to
14 layers
O
R
m-Fold LVDS
signals (Y-Plane)
Final trigger
FR
C
60
FR
C
60
B.Satyanarayana
Similar coincidence logic from Y Plane
signals ( 1F to 4F)
VECC, Kolkata
O
R
December 24, 2005
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Trigger module status
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Being developed by Electronics Division, BARC
Implemented using a FPGA
Major part of logic coded; scalers to be done
Module given for fabrication
Expected to be ready in two months
Testing and debugging (1 month)
B.Satyanarayana
VECC, Kolkata
December 24, 2005
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CAMAC based control module
Generates three sets
of control and hand
shake signals for
selection of DFE
board, readout of
event data and
monitoring of pickup
signals in the selected
board
B.Satyanarayana
VECC, Kolkata
December 24, 2005
12
CAMAC based readout module
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Four serial event data read out channels
Eight monitor data inputs
Serial to parallel conversion of event data
Data written into FIFO buffer
FIFO buffers readout through CAMAC backplane in the
event routine
• Eight selected monitor channels translated into ECL
logic signals
• Rates monitored through ECL input CAMAC scaler
modules
B.Satyanarayana
VECC, Kolkata
December 24, 2005
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Other items
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High voltage supplies (CAEN, SINP)
Low voltage supplies (Local)
Components, cables etc
Commercial/available modules
– TDCs
– Scalers
– CAMAC crates and controllers
• DAQ software on Linux platform
B.Satyanarayana
VECC, Kolkata
December 24, 2005
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Thoughts for final detector
• Expertise from TIFR, BARC, SINP, VECC, IITB,
IGCAR, NSC etc
• Industry ready and active
• Front-end and timing ASICs
• Low rates; high degree of multiplexing possible
• ASIC design process must begin now
• Comparator ASIC work by SINP
• Tools and training of personnel
• Discussion meeting at national level
B.Satyanarayana
VECC, Kolkata
December 24, 2005
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