Transcript Diapositive 1 - ESA Microelectronics Section

Evaluation of a
12 bits Video Processor
for Space Application
J.-Y. Seyler, F. Malou, G. Villalon (
CNES, Toulouse - France )
1st AMICSA Workshop – 2 & 3 October 2006
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Presentation Plan :
 The Context
 The Purpose
 You said « CSP » ???
 CSP Functions
 Preliminary Tests
 Preliminary Selection
 From 5 to 3 candidates
 Characterization Principle
 Measurements Results
 1 possible candidate
 Complementary Tests
 “ Lot Evaluation ” Tests
 Quality, Reliability & Radiations Evaluation
 Electrical Tests
 Radiations Validation
1st AMICSA Workshop – 2 & 3 October 2006
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Context (1/2) :
 In space applications, analog electronics for CCD signals processing
uses usually specifically designed devices such as :
Asics or Hybrid Circuits ...
Today :
• Performances needs are increasing 
( maximum pixel frequency, linearity, noise ... )
• While the mean power consumption should be decreased 
 So, commercial CMOS CCD Signal Processor ( CSP )
are a possible solution to cope with all these constraints.
1st AMICSA Workshop – 2 & 3 October 2006
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Context (2/2) :
 In the last years, low power CMOS CSP where introduced on the market
for wide diffusion applications ( digital imaging, video, … ).
 BUT : according to their incomplete datasheets it is not possible
to accept those devices in a space payloads
without complementary measurements !
 Measurements objectives :
With a specifically developed electronic bench, characterization :
• of Critical Parameters ( linearity, noise )
• and Sensibility to Environmental Influence.
1st AMICSA Workshop – 2 & 3 October 2006
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Purpose :
In order to optimise the performance of the electronics of video
equipments, we have tested several “ Video Processors ”
( or CSP = “ CCD Signal Processor ” or AFE = “ Analog Front End ” ).
1. PRELIMINARY TESTS :
These tests were based on :
•
•
Latchup sensitivity
Electrical performances ( some tests at several temperatures )
 They have then allowed to select one possible candidate.
2. LOT EVALUATION TESTS :
So, we have bought several parts from the same lot ( 2 sub-lots )
and performed a “ Lot Evaluation ” :
•
•
Lot Qualification ( “ COTS ” philosophy )
Radiation sensitivity ( Latchup, Total Dose, Single Event Upset )
1st AMICSA Workshop – 2 & 3 October 2006
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You said : “ CSP ” ??? :
• The Analog Video Signal Processing
• The CSP Function
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Photons
Analog Video Signal Processing :
D
e
t
e
c
t
o
r
Analog
Processing
Electronics
Analog to
Digital
Conversion
Video Chain
Detector
Implementation
Electronics
Interface
to Digital
Devices
CCD
PROCESSOR
Timing
Generator
Power Supply
1 single consumer “ Off-the-shelf ” electronics component may replace several functions 
1st AMICSA Workshop – 2 & 3 October 2006
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You said « CSP » ???
What is an CSP, « CCD Signal Processor » ?
 It is a Integrated Circuit which is usually composed of the
following elements :
–
–
–
–
–
Input DC value compensation ( Clamp ),
Correlated Double Sampling ( CDS ),
Signal scaling by Variable Gain Amplifier ( VGA ),
Analog to Digital Converter ( ADC ),
Offset Calibration Loop based on Dark Pixels.
– Additional functions : DAC, auxiliary A / D…
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CSP Functions :
Gain and A/D Conversion
ADCCLK
CCD
IN
SHP
CDS
VGA
A/D
CONVERTER
CLPDM
SHD
CLPOB
OFFSET
REGISTER
Input Clamp
Correlated Double Sampling
1st AMICSA Workshop – 2 & 3 October 2006
Dark Pixel Offset Correction
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Preliminary Selection :
• Latch-Up sensitivity Test
• Electrical Characterization
• Selection Criteria
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Preliminary Selection :
• Latch-Up sensitivity Test ( CNES Quality Dep t ) :
– Bibliographic survey
– Elimination of several fab-less candidates
 5 types among 2 manufacturers
– Latch-up tests
 3 candidates among 2 manufacturers
• Full Electrical Characterization :
– Inter-calibration with other bench ( on 1 part already tested )
– Tests ( @ SODERN )
 1 only candidate left
1st AMICSA Workshop – 2 & 3 October 2006
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Criteria & Selected CSPs :
• Our need :
• 1 Channel only,
• Resolution = 12 bits,
• 20 MSamples / Second
• Offset calibration loop ( based on dark pixels )
• Programmable Gain : ~ 0  40 dB.
We have eventually selected 3 CSPs :
• Candidate 1 ( Analog Devices )
: 70 mW
• Candidate 2 ( Texas Instruments ) : 80 mW
• Candidate 3 ( Texas Instruments ) : 75 mW, Low Latchup sensitivity
1st AMICSA Workshop – 2 & 3 October 2006
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SEL Sensitivity / LET :
SEL X-section (cm²/dev.)
1E-03
1E-04
1E-05
no event
1E-06
no event
no event
1E-07
10
20
30
40
50
60
70
LET (MeV/mg.cm²)
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Preliminary Tests :
•
•
•
•
Test Bench presentation
General Performances of the CSP
Complementary tests of the candidate
Thermal Characterization & Radiation Tests
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Characterization Principle :
•Pattern Generation
•Bench Configuration
•I/O bench
Palier référence
DAC 16 bits
Valeur pixel
Palier vidéo
Clocks
Synthesis
Control Computer
•Performances computation
•Graphic display
•Storage
10
9
8
7
6
5
4
3
LSB(12)
2
1
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
0
512
1024
1536
2048
2560
3072
3584
4096
Code de sortie de l'AFE
Real Time
recording
CSP under Test
Data exploitation
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Bench :
Video stimuli waveform
Performances :
• 9.25 Mhz maxi pixel frequency
• Better than +/- 2 LSB (12) integ. linearity
Benchmark and Evaluation Board
1st AMICSA Workshop – 2 & 3 October 2006
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General Performances
of the CSP :
• Differential Non Linearity
• Integral Non Linearity
• Noise Performance
1st AMICSA Workshop – 2 & 3 October 2006
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Differential Non Linearity Performance :
N LD p ixel s su r l es pi xel s ut il es
1
1
Non Linéariré Différentielle
0.75
0.5
0.25
Bi
0
0.25
0.5
0.75
1
1
0
500
1000
1500
0
2000
2500
3000
3500
4000
i
long
P as codeur
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Integral Non Linearity Performance :
N LI p ixel s su r l es pi xels u t il es
3.5
3.5
3
Non Linéarité Intégrale
2.5
2
1.5
Bi
1
0.5
0
0.5
1
2
1.5
2
0
500
1000
1500
0
2000
2500
3000
3500
i
long
P as codeur
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4000
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Noise Performance :
Rép art it io n du brui t (en L SB)
1
0.8
0.6
fk
Distri k
0.4
0.2
0
0
0.4
0.6
0.8
1
lower
1.2
1.4
1.6
inter valsk
upper
Bruit en LSB
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Measurements Results :
• Differential Non Linearity performance
• Integral Non Linearity performance
• Noise performance
Comparison versus “ Space application ” requirements :
 Compatible with high performances applications 
 … but with complementary measurements !
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Complementary Tests :
• Complementary Electrical Tests
• Total Dose Tests
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Complementary Tests (1/3) :
• Complementary Electrical Tests :
– Some additional electrical tests ( @ room temp )
– Tests at : - 20 °C, + 25 °C, + 70 °C
Consommation du VSP1221
CSP selon la dose cumulée d’irradiation (7.5 MSPS)
300.0
Some concerns about
dose rate
( “ Rebound Effect ” ? )
250.0
Consommation (mW)
•Total Dose Tests :
200.0
Echantillon 1
150.0
Echantillon 2
Echantillon 3
100.0
50.0
0.0
initial
1st AMICSA Workshop – 2 & 3 October 2006
4.8 krad
7.2 krad
14.4
krad
33 krad
Anealing
24 h
Anealing
168h
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Complementary Tests (2/3) :
– Electrical Tests made at ambient temperature,
and related with project specifications :
• Pleiades Satellites needs
• + Specific tests for next projects
( “ Post Pleiades ” & Scientific Payloads ) :
–
–
–
–
Large Reset peak
Saturated pixel
Clamp efficiency ( V_ref influence for V_util = V_ref = Ct )
Offset correction
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Complementary Tests (3/3) :
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Lot Evaluation :
• Quality, Reliability
• Electrical Tests
• Radiations Validation
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The Future : “ Lot Evaluation ”
(at CNES)
• Procurement of “ Commercial Quality Level ”
& “ Extended ” Temperature Range ( -20°,+85°C )
• Purpose :
 Quality, Reliability & Radiations Evaluation
1st AMICSA Workshop – 2 & 3 October 2006
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Procurement
6P DC0440
11P TID + 5P SEU
DC0501
Performance
Characterization
Construction
Analysis
13P DC0501
Electrical Characterization
-40°C/–20°C / +25°C / +75°C/+125°C
3P
6P DC0501
Radiation Test :
TID + SEU
Serialization
Quality,
Reliability
&
Radiations
Evaluation
750P – DC0501
250P – DC044
13P DC0501
Reference
Life Test
Electrical Measurement
-40°C/+25°C/+125°C
DPA
10P
10P DC0501
1P
Final Report
1st AMICSA Workshop – 2 & 3 October 2006
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Specific Test Bench :
Developed @ CNES Qual. laboratory for :
•
•
FPGA delivers different
digital stimuli which are
transferred through
a 16bits Digital to
Analog Converter
at the input of the CSP.
• Biasing the component ( Stimuli Generation )
• Static & Dynamic performances. EXA3000
•DNL, INL Extraction
CSP
under TEST
FPGA
Ramp
DAC 16 bits
Din
1 > f > 600 MSPS
CCD
Format
The EXA3000
( ATE ) tester ensures
the control signals
generation, the data
reception and the
processing
( parameters extraction )
1st AMICSA Workshop – 2 & 3 October 2006
Pin
• Functional
Characterization :
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
AC
DC
8 Bits DAC
8 Bits DAC
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Electrical Tests :
• Up rating / Electrical characterization at 5 temp. :
- 20 °C / + 25 °C / + 75 °C  conformity with the manufacturer’s
datasheet
- 40 °C & + 125 °C  possibility of temperature range extension ?
• Dynamic Life Test (10 parts) :
–
–
–
–
2000 hours,
T = 125 °C,
Vcc = 3.3 V
Intermediate electrical measurement : 168 h, 500 h, 1000 h
@ Tamb = 25 °C with F = 15 Msps.
– The final measurement will be done at 3 temperatures.
– Final DPA
• Construction Analysis ( 6 parts ) :
 Identify & describe the Front-End and Back-End technologies.
1st AMICSA Workshop – 2 & 3 October 2006
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Radiations Validation :
• Total Ionizing Dose :
– 11 parts ( 8 On, 2 Off, 1 Ref. ) with ONERA DESP Cobalt60 Source
– Total Dose : 15Krad ( Si ) & 30Krad ( 2 lots ) @ 30 rad / h
– Low Dose Rate ( because of the “Rebound Effect”
found after 14 krads in previous TID test )
– Annealing : 24 h / 25 °C + 168 h / 100 °C
All the datasheet parameters : measured at ambient temperature & 15 Msps.
• Heavy Ions Tests :
– Previous tests showed that the CSP is not sensitive to Single Event
Latch-up for a LET of 60 MeV / mg . cm ²
– Single Event Effect ( Transient, Upset or Functional Interrupt )
– UCL ( Belgium ) heavy ions facilities + specific test bench
( stimuli, count, record events ) with TRAD support.
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Conclusion :
At the end of the validation of the lot
(beginning 2007), we will be able to answer
to the question :
 “ Is our selected CSP, coming from
commercial procurement recommended for
usage in our spaceflight applications ??? ”
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