Transcript Conf.Logic for ESA Application

AMICSA 2008 31 August – 02 September
Sintra, Portugal
Multi-Gbit/s Capable 65nm CMOS Ser/Des
Design Analysis for Space Application
Dugoujon, L.1; Hili, L.2; Skoulaxinos, S.3; Papadas, C.3; Baguena,
L.4; Childerhouse, M.5; Tonietto, D.1; Ramet, S.1; Badets, F.1;
Lavastre, S.1; Briand, P.1
1STMicroelectronics
(France); 2ESA (The Netherlands);
3ISD Athens (Greece); 4Thales Alenia Space (France);
5EADS Astrium (United Kingdom)
ST Global Presentation
AMICSA 2008, September 02
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ST Global Presentation
AMICSA 2008, September 02
STMicroelectroics, ISD
EADS-Astrium
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2
ST Global Presentation
AMICSA 2008, September 02
STMicroelectroics, ISD
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3
ST Global Presentation
AMICSA 2008, September 02
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ST Space & HighRel History & Policy
First space supplier ever SCC-B Qualified (1979)
Major ESA QPL contributor
1999: Creation of Rad Hard Design Center in ST-Sicily
Expanding product portfolio
ST Space & HiRel Policy:
Wide & stable Product Range offerings
300krad at High Dose Rate & ELDRS (world leadership).
Top level Heavy Ions requirements
Top Level Space Quality
Develops world business through QML-V Qual (1998)
Full support & commitment to Europe national Space Programs:
« GalileoSat », « NGP », « Digital Divide », « COSMO » , « XMM »
Dedication to custom products support
AMICSA 2008, September 02
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Space Product Portfolio extract
Available:
Classical bipolar Transistor
2N2222’s series
300krad ELDRS-free Bipolar Linear Regulators: RHFL4913, L7913
300krad ELDRS-free Bipolar Op-Amps:
RHF43B
300krad Bipolar fast Op-Amps
RHF300=>RHF350 series
100krad Logic series:
54HC00’, CD4000B’s (Escc)
300krad Logic serie:
54AC00’s
(Qml-V)
300krad 16-bit Bus Interfaces:
54VCXH162244’s (Qml-V)
300krad 12-bit AD-Converter:
RHF1201
(Qml-V)
300kRad 14-bit ADC
RHF1401 Qml-V in 2008.
In the pipe:
Smd Diodes
100 kRad PowerMOS
100kRad ELDRS-free 2N Transistors redesign
1N5822-5819-5811-5806 ‘s
Clock Distributor
RHFLVDS111,
300krad 32-bit Bus Interface
300krad ELDRS-free Quad Op-Amp
300krad ELDRS-free fast Op-Amp
AMICSA 2008, September 02
54VCXH322245 EM avail, qual ‘08
RHF484
RHFS111 of a new RH-SOI techn
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650MHz, EM avail
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ST INSIDE
MSL ROVER
Juno Spacecraft
L = ~9’
JWST Telescope
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Need & constraints for Gbit/s SerDes
Main application:
Next Generation Telecom Satellites Digital Payload
Partnering with European space industry primes:
EADS-Astrium, Thales-Alenia Space
Key objectives of KIPSAT project (under ESA contract):
Assessment of ST 65nm long term reliability
Demonstration of SerDes 6.25Gbit/s performances
Baseline for a space-grade ASIC technology
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System Architecture example
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Payload ASICs constraints
Payload Processor ASIC requirements:
10-30 Millions gates- 3-8Mb RAM - 6Gbit/s
Serial I/Os – 200-400MHz Processing Clock –
Low dissipation – High-Reliability - RadHard –
Hermetic Package – Moderate customization
costs for Manufacturers
Such performances are only achievable with
Deep Sub Micron
ST proposed its CMOS 65nm, commercially
qualified in 2007.
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ESA Requirements / Intrinsic 65nm
10-30 Mgates
400MHz clock
Low power < 10W
>20 x 6.25Gbit/s HSSL
Available before 2011
Non ITAR
TID > 200krad(Si)
No SEL 80MeVcm2/mg
750 kgates/mm2
2GHz stdcells
5.7nW/(MHz x gates)
1.25-7.5GBit/s modules
Production in 2008
Made in Crolles (Isère-F)
No variation 100krad(Si)
OK with process option
SEE<10-10/b/day in geo
15 years opl. lifetime
Viable business model
Efforts needed for SEUs
Achievable
MPW/MLR or Platform
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What? 65nm for Space!
Do we risk in such recent technology?
What about:
Rad-hard capabilities
Reliability
Cost
Design flow
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Rad-hard maximisation
Rad-hard capabilities measured under ESTEC-ST
contracts (ST 130nm, 90nm, 65nm and 45nm)
Usage of process option for SEL (1mask)
Experimental confirmation on worst case supply and
Temp
Validation of « analog » HSLL IP (LC-tank VCO)
Re-use of SEU mitigation techniques (ST patented) on
Std. Cells and clock-trees specificaly developed for
this 65nm platform
Usage of a mix of SRAM or rSRAM (ST patent) cuts to
be defined with end-users
RH by design ST (+CERN) know-how enriched by
end-users cooperation.
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Reliability maximisation
Analysis of reliability figures from Std
qualification
Systematic application of ST DiR methodology
(focusing HCI and NBTI) with dedicated tools for
ageing simulations
Eventual specific layout rules for reliability
enhancement
Study of tighter controls at process level
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Reliability summary for ST 65nm
LEVEL1 (Wafer Level Reliability):
Even with Worst Case test conditions, all but two items
(NBTI+HCI) exceed 15 years spec on test structures.
NBTI + HCI: Accurate simulation methodology +
design guidelines provide means to exceed 15 years
on actual IC.
LEVEL2 (Early Failure Rate + Over Life Test ) :
Qualification step: 8 fails out of ~ 6000 samples. All
explained by defectivity/SPC.
Post-Qual monitoring: 0 fail (10 years) out of ~4000
samples.
Huge enhancement of D0 with the PDF program.
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Device Reliability Modeling
VG+
Goal: Cover all VG/VD domain
HCI
PBTI
VG
Off-state
VD+
GRILLE
GATE
VD
VG+
SUBSTRAT
BULK
Off-state
VD+
NBTI
HCI
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Transistor-Level Reliability Simulation
Flow
Reliability model (Eldo UDRM)
•Extended models
Reliability
parameters
SPICE model
Description of
Transistor Stress
as function of
Activity
Description of
SPICE parameters
evolution as
function of Stress
Netlist
•Age.lib object Library
Aged Results
Simulate Aged
Simulate Fresh
Comparison
Model Parameters
(Fresh)
Aging related
commands
Updated SPICE
parameters
Nominal Results
Stress analysis
Eldo
Stress File
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Optional
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Reliability Modeling/Simulation Flow
NBTI, HCI stress experiments
Multiple Vgs/Vds conditions
Model describing the degradation
f(Ids,Ib,W)-HCI
Extractionof
f(Vgs,Vds,T,L,t)-NBTI
degradation
parameters such as
Vt, gm andIV curves
during stress
ModelSPICE
parameter evolution
Reliability Modeling
Add toSpice model
of degradation of At designer end
STEP 1 Estimation
Different transistors
Evaluation of
degradedSPICE
Iterativ
e
Circuit spice n/l
+
Input stimuli
Reliability Simulation
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Running Simulation
AMICSA22008, September 02
STEP
with degraded models
Compare
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Silicon Validation
Inverter ring in 65nm technology
Simulations similar to HTOL of fab silicon
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NBTI simulation: digital buffer
Note the delay introduced by the NBTI
in comprison to the same buffer
without NBTI
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NBTI: Vth shift
Illustration of the input
threshold shift in I/O buffer
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SERDES principle
/2
Data Slice
Data Slice
Clock Slice
Data Slice
Data Slice
I
Q
3.125GHz
4 to 10 data Slices per Clock Slice
Ref Clk
RX
input
offset
Cancellation
TX
output
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SerDes features
Technology
65nm LP ,7 metal ,triple VT, Dual Gate oxide 50A
Power S.
Single 1V2
Data Rates
1.25, 2.5, 3.125, 3.75, 5, 6.25, 7.5Gbps with a single
156.25 ref. clock. (125Mhz ref clock supported )
IO
Stackability
Power
(mW/Link)
RX equal. adaptive , linear up to 15dB + 4 tap DFE
TX: 5 Tap FIR, programmable
4 links per macro
250 max @7.5Gbps, 200 max @ 5Gbps
Area/Bump
900u x 640u /link ( 10 bumps)
Reference
CEI-6 LR
Use: Long reach backplanes lines
Maturity
IP Test chip fully tested, ASIC products in qualification
Doc
Data sheet available ; CAD views available
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designed for 2-2-2 FCBGA
23
SerDes Packaging constraints
Bump
usage
Power
consumption table
data slice
clock slice
power supply
power supply
Clock + 4 Data slices Bump out
Edge of die
640u
RXP
_LI_
2P
TXP
_LO
_3P
TXP
_LO
_3N
RXP
_LI_
2N
CKP
TXP
_LO
_1P
RXP
_LI_
1P
RXP
_LI_
1N
TXP
_LO
_0P
TXP
_LO
_0P
Rate
RXP
_LI_
0P
5.00
172
200
6.25
187
7.5
201
1.1
1.2
VCC
VSS
VCC
3.125
VSS
VCC
3.75
VSS
VCC
VSS
VCC
VCC
VSS
VSS
VSS
VCC
VSS
VCC
VSS
CP
CN
1.3
VSS
VSS
VCC
VSS
VCC
CN
VCC
VCC
VCC
VSS
VCC
Core side
Core side
480u
Update : 1clock slice support 8 data slices
(tbv)
12 @7.5G
(tbv)
16 @6.25
Bump
1.2
1.25
RXP
_LI_
0N
RT
VCC
VSS
VCC
VSS
VCC
1.1
2.50
VSS
VCC
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VSS
1200u
TXP
_LO
_1P
CKN
TXP
_LO
_2P
900u
RXP
_LI_
3N
TXP
_LO
_2P
RXP
RXP
_LI_
3P
VSS

63
68
250
73
Power at Vod peak =400mV
to ball ratio
Package
notes
Bump
Ball
Signal
1
1
Require 1 Resistor and 1 Cap on package
AVDD
4
1
Designed for FCBGA build up 2-2-2 substrate.
AGND
4
1
VCC
TBD
1
AMICSA 2008, September 02
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1.3
SerDes Terrestrial > Space
Organic fcBGA Pkg, 17x17, 2-2-2, 256 Balls, 1.0 mm ball
pitch
Hermetic package solution under analysis
Target BER <10-18 (on CAT4K legacy backplane)
ESA specs of <10-12 (medias to be defined)
250mW max power @7.5Gbps, 200mW max power @
5Gbps
ESA spec=200mW, slight power reduction under study
Re-simulations with ageing effects and eventual rework
15-20 years verification in worst case conditions
AMICSA 2008, September 02
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SEUs mitigation techniques
Analysis of SerDes critical areas
Replacement of standard dffs by robust dffs
(ST patents)
Use of robust clock-trees (ST patents) where
critical
Implementation of TMV where necessary
Continuous reading of configuration registers
and automatic recovery in case of corruption
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Ser/Des Validation (1)
Astrium has evaluated and tested Texas and Xilinx Ser/Des systems.
Texas TLK2711 – 1.6 to 2.5 Gbps
Tested with parallel clock at 1.6Gbps and 2.5Gbps.
Tested with nominal supply voltage (2.5V) +/-0.1V.
No noticeable correlation was apparent.
Tested with various lengths of differential stripline traces and 50 ohm matched
length coax cable.
Stripline lengths of 10, 15, 20, 30, 40 inches and combinations
thereof.
Tested using built in PRBS (27 -1) in a loop back configuration.
Eye measurements
Jitter measurements
BER measurements
Error free, from 1.6 Gbps to 2.5 Gbps, within a determined distance.
AMICSA 2008, September 02
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Ser/Des Validation (2)
Xilinx ML321 – 3.125 Gbps
Tested at 3.125 Gbps and 2.5Gbps using on-board and external oscillator.
Tested with various lengths of differential stripline traces and 50 ohm
matched length coax cable.
Stripline lengths of 10, 15, 20, 30, 40 inches and combinations
thereof.
Tested using built in PRBS generator using various polynomials in a loop
back configuration with 33% pre-emphasis.
Eye and jitter measurements.
BER measurements..
Error free, at 2.5 & 3.125 Gbps, within
a determined distance, with short PRBS
polynomials.
Xilinx MK322 – 10 Gbps
Tested at 5 Gbps and 10 Gbps with various lengths of differential stripline
traces and 50 ohm matched length coax cable.
Tested using built in PRBS generator using various polynomials in a loop
back configuration with default and optimised pre-emphasis.
Eye and jitter measurements.
BER measurements.
Virtually error free, at 10 Gbps, over shorter distances.
AMICSA 2008, September 02
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Ser/Des Validation (3)
“Quatuor” Validation
Test Quatuor configurations that are likely to be used in telecoms payloads.
Test various parametric configurations, e.g. pre-emphasis, output level, equalization.
Consider requirements for autonomous link establishment and maintenance in space
environment subject to SEE.
Prove that unidirectional links can be established, that link performance
degradations and link loss maybe detected and that links can be re-established.
Test with various media as expected to be used in telecoms payloads.
Test impact of clock quality on measured BER.
Perform eye and jitter measurements.
Estimate best achievable BER (assuming ideal Rx and clock recovery) in the absence
of other noise sources.
Measure BER.
Participate in radiation testing of Quatuor
Advise on the design of evaluation board ensuring direct access to parallel digital
data.
Consider the design of dedicated test hardware, for BER, for link establishment and
maintenance, for SEE testing.
Consider hiring dedicated parallel BER Tester.
AMICSA 2008, September 02
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Validation with TAS (1/1)
Thales Alenia Space has been implementing such kind of
components for a long time, starting with first generation of 400
Mbits/s links, that are now in orbit
More recent payloads required far higher
speeds and Serdes components from
1 Gbits/s to over 3 Gbits/s have been
evaluated in our labs
We are presently working on last
generation of components up to 10 Gbits/s
2 methodologies are being used:
Elaboration of our own test/evaluation breadboard including
proprietary BER measurement environment on specific breadboard
Utilization of commercial tools for BER on breadboard:
BER tester Anritsu 1632A up to 3,2 Gbps
BER tester Agilent N4901A up to 12 Gbps
Thales Alenia Space expertise and means will support the present
HSSL development
AMICSA 2008, September 02
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Cost mitigation
Hi-rel Rad-Hard stdcells & IPs selection
Metal-Customizable Logic
Low
troughput/power
consumption
FPGA
AMICSA 2008, September 02
Structured ASIC
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Full cust. ASIC
31
Conclusions
CMOS 65nm provides needed performances for
next generation satellite telecom payload
processors
NBTI and HCI are well modeled and simulated
TID is not an issue, mitigation of SEUs needed
High performances SerDes derived from a
proven IP used in telecom networking products
Robust dff + clock trees available libraries
End-users participate to demonstrator chip
(4x6.25Gbit/s) definition, trade-offs, CDRs and
tests
2sd phase will target to provide ASIC capability
AMICSA 2008, September 02
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Thank you!
See ST Rad-hard products at
www.st.aerospace.com
AMICSA 2008, September 02
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