Transcript Xilinx Template (light) rev

Xilinx Analog Mixed Signal
XADC Evaluation
Note: Agile Mixed Signal is Now Analog Mixed Signal
Xilinx Training
Welcome
This module introduces the 7 series AMS Targeted Design
Platform
– Evaluate XADC performance
– Demonstrates AMS capabilities
This module provides an overview of XADC Evaluation Graphical
User Interface for evaluating the XADC block
To Learn More About Xilinx Agile Mixed Signal
Related Videos
– What is the Xilinx Agile Mixed Solution?
• For beginners and enthusiasts
– Xilinx AMS EDK Design Flow
• For embedded designers who want to become familiar with the EDK flow
– Xilinx AMS HDL Design Flow
• For digital designers who want to become familiar with HDL flow
AMS Design Flow
1. Evaluate
2. Implement
3. Simulate
Need for Analog Signal Conditioning
The external signal needs to be conditioned to map input range
of XADC (0-1V)
Implement custom circuits to bring down the voltage range of
signal
Use Programmable logic
to customize
• Control logic
• Signal processing
• Calibration
RTD Sensor
7 Series FPGA or Zynq EPP
Photo Sensor
Current & Voltage
sensor
RPM Sensor
Analog Signal
Conditioning
Flexible Analog Interface
• Configure analog inputs
• ADC timing
• Change at any time
XADC
DSP
Evaluate XADC Performance to Match Platform
Needs
Conversion Time
T/H
On-Chip
Sensors
ADC 1
MUX
DIFFERENTIAL ANALOG INPUTS
Acquisition Time
Status
Registers
Control
Registers
T/H
ADC 2
DRP
VP/VN minimum acquisition time ~3 ns
VAUXP/VAUXN minimum acquisition time ~300 ns
ADC
Results
Unipolar and Bipolar and Transfer Functions
On-Chip Sensors
Analog Sensor Compensation in the Digital
Domain
Analog Sensor Output
Linearity
Error
After Digital Correction
After Digital Correction
Calibrate
Gain
& Offset
Errors
Analog Sensor Output
KC705 TDP Facilitates XADC Evaluation for
Performance
AMS Targeted Design Platform
– KC705 evaluation board
– AMS FMC evaluation card
– AMS Targeted Reference Design
– ISE® 13.4 Design Suite
– Documentation
Targeted Reference Design
AMS Evaluation Card
Enables user to evaluate performance of
XADC in all operating modes as
described in XADC User Guide (UG480)
On-board signal source
– Dual, high-quality DAC (AD5065)
– Both single ended and differential
supported
Signal conditioning circuitry
– Two dual OPAMP ICs (ADA4841)
BNC connectors to bring in external
signal generators
External power supply jacks
20-pin header for interfacing to a TDP
Jumpers for routing signal connections
to FPGA
Setup for Evaluating the XADC
Optional External Instrument
(e.g. signal generator)
XADC Evaluation Card
Resources (DACs) for basic testing and
connectors for external instruments
Ribbon cable connection
to “analog header” on KC705
USB
KC705
National Instruments LabView GUI
• XADC settings
• ADC data collection and analysis
Targeted Reference Design
Facilitates evaluation of key performance metrics of Xilinx Analog to
Digital Convertor (XADC)
Demonstrates the capabilities of AMS using the Decimation filter
The design running on the FPGA is built using the Embedded
Development Kit (EDK)
– All blocks represented in the FPGA design are available as IP cores from
Xilinx
XADC Evaluation GUI
Developed using National
Instrument’s LabView run-time
environment
Run key performance tests with
XADC evaluation GUI
– Configure XADC
– Configure signal source on AMS
evaluation card
– Perform time domain and frequency domain analysis of XADC data
– Perform a linearity test
– Demonstrates the capabilities of AMS using the Decimation filter
implemented in the Targeted Reference Design
XADC Evaluation GUI (continued)
DAC
Control
XADC Configuration Control
Sampling
rate
When Simultaneous sampling
modes is selected VAUX0 and
VAUX8 are selected.
XADC On-Chip Sensors
Change the
actual voltage
applied to
FPGA here
XADC Registers Tab
Document the settings
after achieving satisfied
results
AMS Demonstration (Decimation Filter)
Change
Decimation Rate
SNR Being
Improved
Summary
Evaluate the XADC for input voltage range, resolution, and performance
– Input signal to XADC must be conditioned to match the input range of XADC block
– Then evaluate the XADC for performance
7 series AMS TDPs enable XADC evaluation
– ADC Evaluation Kit is bundled with all 7 series TDPs
– XADC Evaluation application provides user friendly GUI for evaluating XADC block
– Pick required XADC settings (attributes) and evaluate performance
Implement the XADC core in your HDL design flow
– Use the documented settings captured during evaluation phase to configure the core
• Customizes the core using the CORE Generator™ interface and generate files for
instantiation and simulation
– Write HDL code to perform autonomous operation on XADC for sensing the analog input
• Refer to the XADC User Guide (UG480) for more information on XADC operating modes and
timing
Where Can I Learn More?
Learn more at www.xilinx.com/AMS
– Agile Mixed Signal white paper (WP392)
– XADC User Guide (UG480)
– Watch more videos of Xilinx AMS
Visit www.xilinx.com/innovation/7-series-fpgas.htm
– Application examples
– New 7 series documentation
 Xilinx training courses
– www.xilinx.com/training
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Basic FPGA architecture, basic HDL coding techniques, and other free
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