Transcript Xilinx Template (light) rev

Xilinx Analog Mixed Signal Solution
HDL Design Flow
Note: Agile Mixed Signal is Now Analog Mixed Signal
Xilinx Training
Welcome
If you are a FPGA designer, this module introduces the HDL flow
for Xilinx Agile Mixed Signal solutions
This module will list some key features of the XADC core that are
enabled by Xilinx Agile Mixed Signal solutions
To Learn More About Xilinx Agile Mixed Signal
Related Videos
– What is the Xilinx Agile Mixed Signal Solution?
• For beginners and enthusiasts
– Xilinx AMS EDK Design Flow
• For embedded designers who want to become familiar with the EDK flow
– Xilinx AMS XADC Evaluation
• For designers who want to know how the XADC interface can be evaluated for
their mixed signal application
Implementing XADC in your Design
1. Evaluate
• XADC
evaluation kit is
bundled with all
7 series TDPs
• Choose required
XADC settings
and evaluate
2. Instantiate
3. Simulate
• Set attributes
based on
evaluation and
connect I/O
• Customize
analog interface
using XADC
Wizard
Edit Settings
• Simulate HW
(XADC & FPGA
logic) using
analog stimulus
file
• Use HW in the
loop with ISim to
verify prototype
Evaluating the XADC
Optional External Instrument
(e.g. signal generator)
123.456
#1
XADC Evaluation Card
Resources (DACs) for basic testing and
connectors for external instruments
Ribbon cable connection
to “analog header” on KC705
USB
KC705
National Instruments LabView GUI
• XADC settings
• ADC data collection and analysis
1 – Evaluate XADC Settings
XADC LogiCORE IP
Typically customizable
Fully tested, documented,
and supported by Xilinx
Unlicensed and provided for
free with Xilinx software
VHDL and Verilog flow
support for several EDA
tools
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XADC LogiCORE IP
7 Series XADC
ADC 1
T/H
ADC 2
XADC attributes
initialize the
XADC registers
(settings)
Registers
T/H
MUX
On-Chip
Sensors
1.25V
XADC registers / settings can
also be accessed at any time via
the FPGA fabric
XADC block I/O
Instantiating the XADC
XADC instantiation in
language templates
Configure the XADC
initialize registers by
setting attributes
Connect up the
XADC I/O
2 – Instantiate the XADC
XADC and CORE Generator Tool Integration
A GUI allows central access to LogiCORE™ IP products, as well
as
– Data sheets
– Customizable parameters
 The CORE Generator tool is available as a standalone application
– Launched via Programs > Xilinx ISE Design Suite > ISE Design Tools >
Tools > CORE Generator
 Can be launched from the ISE® Project Navigator and
PlanAhead™ software tools
Interfaces with design entry tools
– Creates instantiation templates for HDL-based designs
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Running the CORE Generator Tool
From the Project Navigator
– Select Project > New Source
– Select IP (CORE Generator &
Architecture Wizard), enter a
filename, and click Next
– Expand FPGA Features and
Design > XADC and select
XADC Wizard
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Running the CORE Generator Tool (continued)
From the PlanAhead
software
– Select Project Manager >
IP Catalog
– In the IP Catalog window,
expand FPGA Features
and Design > XADC and
select XADC Wizard
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XADC Wizard Simplifies HDL Instantiation
Connect XADC I/O and
set attributes using GUI
XADC Wizard User Guide
Click Generate
to generate core
Adding the XADC Core to the FPGA Design
XCO file included in
design hierarchy
XCO file associated
to project
Customize and
regenerate the core
Adding the instantiation
templates to HDL
VHO or VEO templates
for HDL instantiation
XADC Implementation
Code autonomous logic to read and write
to the XADC via the Dynamic
Reconfiguration Port (DRP)
Refer to the 7 Series XADC User Guide
(UG480) to determine the different
operating modes of XADC and DRP timing
information
Xilinx tools provide a graphical view of
how XADC is used in FPGA designs
UG480
Simulation and Verification
Text file contains analog
information (sensors,
external voltages, etc.) that
can be introduced into the
simulation by UNISIM
3 – Simulate XADC (Analog) and Digital
Associating Analog Stimulus to XADC Model
Associating analog
stimulus file as attribute in
XADC HDL instantiation
Associating analog
stimulus file to XADC
model in XADC CORE
Generator Wizard
Simulation Example
Stimulus File Example
Analog information read
in directly by model not
the testbench
HDL
Testbench
UNISIM
Download Example with UG480:
ug480_7Series_XADC.zip
Summary
1.
Evaluate the XADC for performance and settings
– XADC Evaluation Kit is bundled with all 7 series TDPs
– Pick required XADC settings (attributes) and evaluate
performance
2.
Implement the XADC core in your HDL design flow
– CORE generator tool’s XADC Wizard simplifies
configuration
• Customizes the core and generates files for instantiation and
simulation
• Refer to the XADC Wizard User Guide (UG772) to configure the core.
• Generate XCO file that can be instantiated in your HDL
– Write HDL code to perform autonomous operation on XADC for sensing the analog input
• Refer to the XADC User Guide (UG480) for more information on XADC operating modes and
timing
3.
Simulate the XADC in an HDL simulator
– UNISIM (Verilog and VHDL) model for XADC
– Support for analog test vectors using an analog stimulus file
Where Can I Learn More?
Learn more at www.xilinx.com/AMS
– Agile Mixed Signal white paper (WP392)
– XADC User Guide (UG480)
– Watch more videos of Xilinx AMS
Visit www.xilinx.com/innovation/7-series-fpgas.htm
– Application examples
– New 7 series documentation
Xilinx training courses
– www.xilinx.com/training
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Xilinx tools and FPGA architecture courses
Hardware description language courses
7 series design courses
Basic FPGA architecture, basic HDL coding techniques, and other free
Videos
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