Transcript Šiuolaikinių kompiuterių architektūra

COMPUTER
ARCHITECTURE
(for Erasmus students)
Assoc.Prof. Stasys Maciulevičius
Computer Dept.
[email protected]
[email protected]
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Input/output
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We will define input/output as a subsystem of
components that moves coded data between
external devices and a host system, consisting of a
CPU and main memory.
I/O subsystems include, but are not limited to:
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Blocks of main memory that are devoted to I/O functions
Buses that provide the means of moving data into and out of
the system
Control modules in the host and in peripheral devices
Interfaces to external components such as keyboards and disks
Cabling or communications links between the host system and
its peripherals
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Computer and its I/O devices
CPU
Interrupt requests
Cache
I/O bus
I/O
controller
Main
memory
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HD
HD
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I/O
controller
Graphic
unit
I/O
controller
LAN
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Input/output problems
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The possibility to connect various peripheral
devices
Performing of input/output operations parallel
with operations in processor
Maximally simplified programming of input and
output processes
The response to various emergency situations
and problems in peripheral equipment
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Problem-solving ways
Modularity of peripheral equipment
(constructive completeness, a simple
connection)
 Uniform data formats
 Unified interface
 Unified instruction formats and types
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Addressing of peripheral equipment
and I/O instructions
a) separate address space (PDP)
b) overlapping address spaces
Instructions:
a) move – universal (both for memory access and
peripheral equipment)
b) load/store - for memory access, in/out - for
peripheral equipment access
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Transfer of information
The transfer of information between the
processor and a peripheral consists of the
following steps:
1. Selection of the device and checking the
device for readiness
2. Transfer initiation, when the device is ready
3. Information transfer
4. Conclusion
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General I/O structure
Memory
Address bus
Data bus
CPU
Control and status
Device
selection
lines
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Interface
Interface
Interface
Device 1
Device 2
Device n
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Device interface
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A device interface is unique to a particular
device since each device is unique with respect
to its data representation and read-write
operational characteristics
The major functions of a device interface are
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Timing
 Control
 Data conversion
 Error detection and correction
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Device interface
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The timing and control aspects correspond to the
manipulation of control and status signals to bring about
the data transfer
In addition, the operating speed difference between the
CPU and the device must be compensated for by the
interface
In general, data conversion from one code to the other is
needed, since each device (or the medium on which
data are represented) may use a different code to
represent data
Errors occur during transmission and must be detected
and if possible corrected by the interface
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Device interface
Device
selection
Control
Status
(from CPU) (to CPU)
Decoder
Control
(selector)
Status
Commands
Device
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Status
Data
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Data
lines
Device
controller
Transducer
Buffer
Binary
data
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Device interface
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Device selection is performed by address
decoding
The transducer converts the data represented on
the I/O medium (tape, disk, etc.) into the binary
format and stores it in the data buffer, if the
device is an input device
In the case of an output device, the CPU sends
data into the buffer and the transducer converts
this binary data into a format suitable for output
onto the external medium
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Programmed I/O
a) unconditional I/O
b) conditional I/O
in/out port
Ready?
No
Yes
in/out port
Port – address of peripheral device
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Programmed I/O
c) interrupt mode I/O
Preparation of
information
exchange
Preparation of
interrupt system
INTR
Main
program
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INTR
...
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Exchange
subprogram
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Ports
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Input port – any data source that can be
selected performing the input command
Output port – any data receiver that can
be selected performing the output
command
Port addresses are sent through the address bus
(or part of it)
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I/O channels
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I/O channel is a generic term that refers to a
high-performance input/output architecture that
is implemented in various forms on a number
of computer architectures, especially on
mainframe computers
In the past they were generally implemented
with a custom processor, known alternately as
I/O processor or peripheral processor
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Classic: IBM I/O channels
Processor
Main
memory
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I/O channel
I/O
controller
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I/O channel
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A channel is an independent hardware component that
coordinates all I/O to a set of controllers or devices
The CPU of a system that uses channel I/O typically has
only one machine instruction for input and output; this
instruction is used to pass input/output commands to the
specialized I/O hardware in the form of channel
programs
I/O thereafter proceeds without intervention from the
CPU until an event requiring notification of the operating
system occurs, at which point the I/O hardware signals
an interrupt to the CPU
Each channel may support one or more controllers
and/or devices
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I/O channel
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A channel program is a sequence of I/O instructions
executed by the input/output channel processor in the
IBM System/360 and subsequent architectures
The channel program consists of one or more channel
command words
A channel command word (CCW) is an instruction for a
specialized I/O channel processor
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Main functions of I/O channel
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to address the data array in memory
to set the length of data array
to form memory addresses
to calculate volume of data transmitted
to determine the end of I/O operation
to buffer data during tansfer
to change data formats
to minimize the processor participation in I/O
to form interrupt requests
to transfer information about the status of
peripheral device
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Direct memory access (DMA)
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The programmed and interrupt mode I/O structures
transfer data from the device into or out of a CPU register
Direct memory access (DMA) is a feature of modern
computers and microprocessors that allows certain
hardware subsystems within the computer to access
system memory for reading and/or writing independently
of the CPU
Many hardware systems use DMA including disk drive
controllers, graphics cards, network cards, and sound
cards
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Direct memory access
CPU inicializes
DMA, setting
DMA controller
CPU
executes
some
process
...
Cycle
steeling
DMA
controls
data
exchange
INTR
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Direct memory access
The sequence of events during a DMA transfer:
1.
2.
CPU initializes DMA controller, setting AR (Address
Register), WCR (Word Count Register) and sends to DMA
controller command to start data transmission; continues
processing
If WCR0, DMA controller gathers data; when word is
ready for transfer, holds CPU (i.e., “steals” a memory
cycle); if WCR=0, sends transfer-complete interrupt to
CPU
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Direct memory access
3.
4.
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CPU continues with any processing that does not need a
memory access; if memory access is needed, tries to
acquire a memory cycle if DMA controller is not accessing
the memory
DMA controller transfers data; releases the memory;
decrements WCR; increments AR; goes to step 2
DMA controllers can be either dedicated to one
device or shared among several input/output
devices
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DMA controller
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Standard DMA transfers are managed by the DMA
controller, built into the system chipset on modern PCs
The original PC and XT had one of these controllers and
supported 4 DMA channels, 0 to 3
Starting with the IBM AT, a second DMA controller was
added
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DMA controller (8237A)
0 channel
D
Data bus
buffer
CAR (16)
BAR (16)
DREQ0
DACK0
CWR (16)
WCR (16)
MR (6)
Control unit
1 channel
DREQ1
TR(16)
DACK1
Control
signals
Mode control
block
2 channel
DREQ2
DACK2
CR(8)
SR(8)
RR(4)
3 channel
MASK(4)
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DREQ3
DACK3
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Registers and modes
Registers:
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CR – Command Register
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SR – Status Register
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CAR – Current Address Register
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BAR – Basic Address Register
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CWR – Current WordCount Reg.
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WCR – Basic WordCount Reg.
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SR – Request Register
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MASK – Mask Register
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DMA operation
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The multimode DMA controller issues a HRQ to the processor
whenever there is at least one valid DMA request from a
peripheral device. When the processor replies with a HLDA
signal, the 8237A takes control of the address bus, the data
bus and the control bus
The address for the first transfer operation comes out in two
bytes - the least significant 8 bits on the eight address outputs
and the most significant 8 bits on the data bus
The contents of the data bus are then latched into an 8-bit
latch to complete the full 16 bits of the address bus
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DMA operation modes
DMA service will take place in one of four modes:
 Single Transfer Mode. In Single Transfer mode the device is
programmed to make one transfer only. The word count will
be decremented and the address decremented or
incremented following each transfer. When the word count
``rolls over'' from zero to FFFFH, a Terminal Count (TC) will
cause an Autoinitialize if the channel has been programmed
to do so
 Block Transfer Mode. In Block Transfer mode the device is
activated by DREQ to continue making transfers during the
service until a TC, caused by word count going to FFFFH, or
an external End of Process (EOP) is encountered
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DMA operation modes
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Demand Transfer Mode. In Demand Transfer mode the
device is programmed to continue making transfers until a TC
or external EOP is encountered or until DREQ goes inact.
Thus transfers may continue until the I/O device has
exhausted its data capacity
Cascade Mode. This mode is used to cascade more than
one 8237A together for simple system expansion. The HRQ
and HLDA signals from the additional 8237A are connected to
the DREQ and DACK signals of a channel of the initial
8237A. This allows the DMA requests of the additional device
to propagate through the priority network circuitry of the
preceding device
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Cascading
Slaves
Master
CPU
HRQ DREQ
HLDA DACK
8237A
HRQ
HLDA
8237A
DREQ
DACK
HRQ
HLDA
8237A
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