Transcript Slide 1

Computer Organization
Lecture Set – 03
Chapter 3
Huei-Yung Lin
Roadmap for the Term: Major Topics
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Computer Systems Overview
Technology Trends
Instruction Sets (and Software)
Logic and Arithmetic \
Performance
Processor Implementation
Memory Systems
Input/Output
CCUEE
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Review: Positional Notation of Numbers
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Example: Binary (base 10) numbers
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Base = 2
Digits = {0,1} Note “bit” == “Binary digit”
N = 1001two = 1  20 + 0  21 + 0  22 + 1  23 = 1ten + 8ten = 9ten
Example: Hexadecimal (base 16) numbers
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CCUEE
Base = 16
Digits = {0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F}
N = 1A3Fhex = 15  160 + 3  161 + 10  162 + 1  163
= 15ten + 48ten + 2560ten + 4096ten = 6719ten
= 0001101000111111two
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Range of Unsigned Binary Numbers
CCUEE
Number of Digits
Smallest Value
Largest Value
n
0
2n-1
8
0
28-1 = 255
16
0
216-1 = 65,535
32
0
232-1 =
4,294,967,295
64
0
264-1 =
1.8446 X 1019
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Review: Unsigned vs. Signed Numbers
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Basic binary - allows representation of non-negative
numbers only
In C, Java, etc:
unsigned int x;
Useful for unsigned quantities like addresses
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Most of us need negative numbers, too!
In C, Java, etc:
int x;
How can we do this?
… Use a signed representation
CCUEE
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Signed Number Representations
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Sign/Magnitude
Two’s Complement - the one almost everyone uses
One’s Complement
Biased - used for exponent sign in Floating Point
CCUEE
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Sign/Magnitude Representation
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Approach: Use binary number and added sign bit
1
0 0 1 1 0 0 1
Sign
Magnitude
= -25
Problems:
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Two values of zero
Difficult to implement in hardware - consider addition
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CCUEE
Must first check signs of operands
Then compute value
Then compute sign of result
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Two’s Complement Representation
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Goal: make the hardware easy to design
Approach: explicitly represent result of “borrow” in subtract
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CCUEE
Borrow results in “leading 1’s”
Weight leftmost “sign bit” with -2n-1
Use sign bit to represent “last borrow”
N = 1111tc = 1  20 + 1  21 + 1  22 + 1  -23 = 7ten + -8ten = -1ten
N = 1001tc = 1  20 + 0  21 + 0  22 + 1  -23 = 1ten + -8ten = -7ten
N = 0101tc = 1  20 + 0  21 + 1  22 + 0  -23 = 1ten + 4ten = 5ten
All negative numbers have a “1” in the sign bit
Single representation of zero
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Range of Two’s Complement Numbers
CCUEE
Number of Digits
Most Negative
Value
Most Positive
Value
n
-2n-1
+2 n-1-1
8
-27 = -128
+2 7-1 = +127
16
-215 = -32,768
+2 15-1 = +32,767
32
-231 =
-2,147,483,648
+2 31-1 =
+2,147,483,647
64
-263 =
-9.22 X 1018
+2 63-1 =
+9.22 X 1018
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Negating Two’s Complement Numbers
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Important shortcut:
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Result:
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Invert the individual bits
Add 1
Two’s complement representation of negated number!
Examples (with 4 bits):
- (0111) = 1000+1 = 1001
- (1100) = 0011+1 = 0100
- (1111) = 0000+1 = 0001
CCUEE
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-7
+4
+1
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Other Signed Binary Representations
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One’s Complement
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Use one’s complement (inverted bits) to represent negated numbers
+1 = 0001
-1 = Invert(0001) = 1110
Problem: two values of zero (0000, 1111)
Biased
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Add a bias (offset) to all numbers
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CCUEE
Most negative number:
Zero:
Most positive number:
000...0 = -2n-1
100...0 = 0
111...1 = +2n-1-1
Used for exponent in IEEE floating point representation
(more about this later)
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Sign Extension
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To convert a “narrower” signed number to a “wider” one:
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Copy the bits of the narrower number into the lower bits
Copy the sign bit from the narrower number into all of the
remaining bits of the result
Example: Converting signed 8-bit byte to 32-bit word:
CCUEE
11111010
Orignal byte: -6
111111111111111111111111 11111010
Result word: -6
00101011
Orignal byte: 45
000000000000000000000000 00101011
Result word: 45
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Zero-Padding - for Unsigned Numbers
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To convert a “narrower” unsigned number to a “wider”
one
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Copy the bits of the narrower number into the lower bits
Copy “zeros” into upper bits of wider number
00101011
Orignal byte: 45
000000000000000000000000 00101011
Result word: 45
zeros
zeros
CCUEE
11000001
Orignal byte: 193
000000000000000000000000 11000001
Result word: 193
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Sign Extension in MIPS
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Load-byte (lb) instruction
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Loads an 8-bit signed number from memory
Performs sign extension before placing in 32-bit register
Load-byte unsigned (lbu)
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CCUEE
Loads an 8-bit unsigned number (e.g., ASCII character) from
memory
No sign extension - places byte with leading “0’s” in 32-bit
register
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Sign Extension in MIPS I-Format
Instructions
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I-Format Instructions have 16-bit immediate field
MIPS operations are defined on 32-bit registers
Sign extension performed on immediate operands “when
it makes sense”
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CCUEE
Sign extension used for addi, beq, bne, ...
Zero-padding used for andi, ori, ...
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Signed & Unsigned Comparisons
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MIPS provides two versions of “set less than”
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slt - signed comparison - useful when comparing signed
numbers
sltu - unsigned comparison - useful when comparing
unsigned numbers (e.g. addresses)
Example: suppose
$s0=1111 1111 1111 1111 1111 1111 1111 1111
$s1=0000 0000 0000 0000 0000 0000 0000 0001
what do the following instructions do?
CCUEE
sltu $t0, $s0, $s1
231-1 > 1, so $t0 = 0
slt
-1 < 1, so $t1 = 1
$t1, $s0, $s1
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Review: Binary Addition
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Key building block: Full Adder
Ai Bi
Ci+1 Ci
Si
CCUEE
Ai Bi Ci
Si
Ci+1
0
0
0
0
1
1
1
1
0
1
1
0
1
0
0
1
0
0
0
1
0
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
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Multiple-Bit Adders
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String together Full Adders to form a Ripple Adder
A3 B3
C4 C3
S3
CCUEE
A2 B2
C3 C2
S2
A1 B1
C2 C1
S1
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A0 B0
C1 C0
S0
0
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How to Subtract with an Adder
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Recall
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Definition of subtraction: A-B = A + (-B)
Two’s Complement Negation Shortcut
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-B = bit_invert(B)+1
A3 B3
C4 C3
S3
CCUEE
A2 B2
C3 C2
S2
A1 B1
C2 C1
S1
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A0 B0
C1 C0
S0
1
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Designing an Adder/Subtractor
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Recall
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Definition of subtraction: A-B = A + (-B)
Two’s Complement Negation Shortcut
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-B = bit_invert(B)+1
Control
Add/Sub
0 to add
A3 B3
C4 C3
S3
CCUEE
A2 B2
C3 C2
S2
A1 B1
C2 C1
S1
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A0 B0
C1 C0
S0
1 to subtract
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Overflow in Addition & Subtraction
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Overflow - occurs when not enough bits are available to
represent the result
Example: unsigned 32-bit result ≥ 232
Example: signed 32-bit result < -231 or ≥ 231
Detecting overflow - look for different signs in operands
vs. result:
Operation
CCUEE
Operand A Operand B
Result
A+B
≥0
≥0
<0
A+B
<0
<0
≥0
A-B
≥0
<0
<0
A-B
<0
≥0
≥0
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What to Do When Overflow Occurs?
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In some languages (e.g., C, Java) - nothing
(“responsibility left to the programmer”)
In other languages (e.g. Ada, Fortran) - “notify
programmer” through runtime exception
How MIPS handles overflow:
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CCUEE
add, sub, addi - runtime exception on overflow
addu, subu, addiu - no runtime exception on overflow
Note functions otherwise identical to add, sub, addi …
including sign extension in addiu!
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Delay in Adders
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Review: full adder equations
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Sum:
Carry:
si = ai XOR bi XOR ci
ci+1 = ai  bi + ai  ci + bi  ci
Delay estimate: 32-bit ripple add
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Worst case: A0 or B0 to C32 (or S31)
Carry delay - each stage: 2 gate delays
Total delay: 64 gate delays - too high!
A3 B3
C4 C3
S3
CCUEE
A2 B2
C3 C2
S2
A1 B1
C2 C1
S1
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A0 B0
C1 C0
S0
0
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Speeding up Carry - Carry Lookahead
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Key idea: trade off delay, amount of logic used
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11
Define two signals for each adder stage:
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Benefit: Faster addition
Cost: much more logic
Generate
Propagate
gi = ai  bi
pi = ai + bi
11
10
A0 B0
C1 C0
S0
X
1
Why use these names?
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CCUEE
Adder i will always generate a carry if ai, bi both true
Adder i will propagate a carry input if either or both ai, bi true
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Carry Lookahead (cont’d)
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Now rewrite carry output as function of ai,bi,pi,gi
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Original eqn:
New eqn:
ci+1 = ai  bi + ai  ci + bi  ci
ci+1 = gi + pi  ci
"Flatten" carry function in terms of gi, pi
c1 = g0 + p0  c0
c2 = g1 + p1  c1
= g1 + p1 (g0 + p0  g0 ) = g1 + p1  g0 + p1  p0  c0
c3 = g2 + p2  g1 + p2  p1  g0 + p2  p1  p0  c0
c4 = g3 + p3  g2 + p3  p2  g1 + p3  p2  p1  g0 + p3  p2  p1  p0  c0
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Add carry lookahead logic that computes c1-c4
in terms of p0-p3 and g0-g3
CCUEE
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Using Carry Lookahead
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Practical computation for 4-bit adders, but...
Too expensive for 16 bits or 32 bits!
a3
b3
c3
p3 g3 s3
p3 g3
Carry Out
CCUEE
c4
P0 G 0
a2
b2
c2
p2 g2 s2
c3
p2 g2
a1
b1
c1
p1 g1 s1
c2
p1 g1
Carry Lookahead Unit
Computer Organization
a0
b0
c0
p0 g0 s0
c1
Carry In
p0 g0
c0
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Using Carry Lookahead
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Cost a limiting factor
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Practical computation for 4-bit adders, but...
Too expensive for 16 bits or 32 bits!
Alternative: Combine 4-bit Carry-Lookahead Adders
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CCUEE
Ripple/Lookahead - string together CLAs
Group-Lookahead - add another level of lookahead
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Ripple/Lookahead Adder
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String together CLA’s
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Faster than ripple adder, but…
Still long delays
a15-a12 b15-b12
4
4
A
c4
4
B
c0
CLA
c4
a7-a4
4
A
S
B
s15-s12
4
A
c0
CLA
b7-b4
4
c4
B
s11-s8
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b3-b0
4
4
c0
4
4
s7-s4
s3-s0
S
4
a3-a0
A
B
c4 CLA c0
S
CLA
S
4
CCUEE
a11-a8 b11-b8
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Group Carry-Lookahead
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Approach: use carry lookahead for 4-bit groups
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“Super Propagate” equations:
P0 = p3*p2*p1*p0
P1 = p7*p6*p5*p4
P2 = p11*p10*p9*p8
P3 = p15*p14*p13*p12
“Super Generate” equations:
G0 = g3 + (p3*g2) + (p3*p2* g1) + (p3*p2 *p1 * g0)
G1 = g7 + (p7*g6) + (p7*p6* g5) + (p7*p6 *p5 * g4)
G2 = g11 + (p11*g10) + (p11*p10* g9) + (p11*p10 *p9 * g8)
G3 = g15 + (p15*g14) + (p15*p14* g13) + (p15*p14 *p13 * g12)
Combine groups using second level
CCUEE
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Group Carry-Lookahead
a15-a12 b15-b12
4
4
a11-a8 b11-b8
4
4
a3-a0
b3-b0
4
4
A
B
CLA c0
P G
S
A
B
CLA c0
P G
S
A
B
CLA c0
P G
S
4
4
4
4
s11-s8
s7-s4
s3-s0
P 3 G3
CCUEE
4
b7-b4
A
B
CLA c0
P G
S
s15-s12
c16
4
a7-a4
C4
C3 P2 G2
C2 P1 G1
C1 P0 G0
Group Carry Lookahead Unit
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Delay Comparison - 16 Bit Adder
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Ripple Adder
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2 gate delays per bit
16 bits
Total: 32 gate delays
Group Lookahead Adder
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CCUEE
Generating C4 (c16) - 2 gate delays from Pi, Gi
Generating Pi, Gi - 2 gate delays from pi, gi
Generating pi, gi - 1 gate delay from ai, bi
Total: 2 + 2 + 1 = 5 gate delays
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Arithmetic-Logic Units
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Combinational logic element that performs multiple
functions:
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Arithmetic: add, subtract
Logical: AND, OR
A
ALU
F(A,B)
B
Operation
Select
CCUEE
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Constructing an ALU - First Cut
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Construct in bit slices, like the ripple adder
Add gates, multiplexer for logic functions, subtract
CCUEE
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ALU Design - Putting it Together
A31
B31
A1
B1
A0
B0
Ai
Ci+1
Bi
Ai
Ci+1
Bi
Ai
Ci+1
Bi
Ci
SEL
ALU31
Si
S31
INV
Ci
SEL
ALU1
Si
INV
S1
Ci
SEL
ALU0
Si
O pe rati on
C arryIn
INV
S0
Bi n ve rt
CCUEE
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Overflow Detection in ALUs
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Overflow occurs when conditions in Fig. 3.3 are met
Ci +1
Problem B.25: equivalent to testing cmsb+1 ≠ cmsb
A31
B31
A1
B1
A0
B0
Ai
Bi
Ai
Bi
Ai
Bi
Ci+1
Ci
SEL
ALU31
Si
S31
INV
Ci+1
Ci
SEL
ALU1
Si
INV
S1
Ci+1
Ci
SEL
ALU0
Si
O pe rati on
C arryIn
INV
S0
Bi n ve rt
O FLO
CCUEE
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Supporting the MIPS slt Instruction
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Want result of 000…001 when A < B
Modify bit slice hardware
CCUEE
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Supporting the MIPS slt Instruction
Add additional multiplexer input, “Less” to slice
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Bit 31: 0
•
•
•
Bit 1: 0
Bit 0: 1 if A<B
CCUEE
Set (MSB only)
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Supporting the MIPS slt Instruction
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Feed “Set” to “Less” input of LSB
It’s actually more complicated than this because of
overflow - see text
0 A31 B31
Less Ai
Ci+1
Ci
SEL
ALU31
Set
Bi
Si
S31
INV
0
A1 B1
Less Ai
Ci+1
Bi
Ci
SEL
ALU1
Si
INV
S1
A0 V0
Less Ai
Ci+1
Bi
Ci
SEL
ALU0
Si
O pe rati on
C arryIn
INV
S0
Bi n ve rt
CCUEE
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Supporting the MIPS slt Instruction
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Set “less” to “00….01” when result less than zero
Details - see Fig. B.5.10, B.5.11 pp. B-33 - B-34
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CCUEE
Use sign bit - “pass around” to LSB of “less”
Complicated by overflow conditions
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Final Result: ALU Function
ALU Operation
ALU control input
000
001
010
110
111
Function
AND
OR
add
subtract
set on less than
A
ALU
B
Zero
Result
Overflow
CarryOut
CCUEE
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Multiplication
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Basic algorithm analogous to decimal multiplication
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Break multiplier into digits
Multiply one digit at a time;
shift multiplicand to form partial products
Create product as sum of partial products
Multiplicand
Multiplier
Product

CCUEE
0110
 0011
0110
0110
0000
0000
00010010
(6)
(3)
Partial Products
(18)
n bit multiplicand  m bit multiplier = (n+m) bit product
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Multiplier Hardware
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Sequential
Combinational
CCUEE
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Sequential Multiplier - First Version
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Multiplicand shifts left
Multiplier shifts right
Sample LSB of multiplier to decide whether to add
Multiplicand (64 bits)
Shift Left
Multiplier (32 bits)
Shift Right
LSB
64-bit ALU
Control
Product (64 bits)
Write
CCUEE
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Algorithm - 1st Cut Multiplier
START
Multiplier0=1
1. Test
MPY0
Multiplier0=0
1a. Add MCND to PROD
Place result in PROD
2. Shift MCND left 1 bit
2. Shift MPY right 1 bit
32nd
Repitition?
DONE
CCUEE
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Animation - 1st Cut Multiplier
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Multiplicand shifts left
Multiplier shifts right
Sample LSB of multiplier to decide whether to add
Multiplicand Multiplicand
Multiplicand
Multiplicand
Multiplicand
Multiplier
LSB
64-bit ALU
Control
Product (64 bits)
Write
CCUEE
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Sequential Multiplier - 2nd Version
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Observation: we’re only adding 32 bits at a time
Clever idea: Why not...
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Hold the multiplicand still and…
Shift the product right!
Multiplicand
(32 bits)
Multiplier (32 bits)
Shift Right
LSB
32-bit ALU
Shift Right
Control
LHPROD
ProductRHPROD
(32 bits) (64 bits)
(32 bits)
Write
CCUEE
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Algorithm - 2nd Version Multiplier
START
Multiplier0=1
1. Test
MPY0
Multiplier0=0
1a. Add MCND to left half of PROD
Place result in left half of PROD
2. Shift PROD right 1 bit
2. Shift MPY right 1 bit
32nd
Repitition?
No: <32 Repititions
Yes: 32 Repititions
DONE
CCUEE
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Sequential Multiplier - 3nd Version

Observation: we can store the multiplier and product in the same
register!
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As multiplier shifts out….
Product shifts in
Multiplicand
(32 bits)
32-bit ALU
Shift Right
Control
MP/RHPROD
Product
LHPROD
MPY (initial)
(32 bits) (64 bits)
(32 bits)
Write
LSB
CCUEE
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Algorithm - 3rd Version Multiplier
START
0. LOAD MPY in right half of PROD
Product0=1
1. Test
PROD0
Product0=0
1a. Add MCND to left half of PROD
Place result in left half of PROD
2. Shift PROD right 1 bit
32nd
Repitition?
No: <32 Repititions
Yes: 32 Repititions
DONE
CCUEE
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Multiply Instructions in MIPS
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MIPS adds new registers for product result:
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MIPS multiply instructions
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Hi - upper 32 bits of product
Lo - lower 32 bits of product
mult $s0, $s1
multu $s0, $s1
Accessing Hi, Lo registers
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CCUEE
mfhi $s1
mflo $s1
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Division Overview
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Grammar school algorithm: long division
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Subtract shifted divisor from dividend when it “fits”
Quotient bit: 1 or 0
Question: how can hardware tell “when it fits?”
1001
Divisor 1000 1001010
-1000
1010
-1000
10
Quotient
Dividend
Remainder
Dividend = Quotient  Divisor + Remainder
CCUEE
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Division Hardware - 1st Version


Shift register moves divisor (DIVR) to right
ALU subtracts DIVR, then restores (adds back)
if REM < 0 (i.e. divisor was “too big”)
Divisor DIVR (64 bits)
Shift R
LSB
QUOT
(32 bits) Shift L
64-bit ALU
ADD/
SUB
Control
Remainder REM (64 bits)
Write
Sign bit (REM<0)
CCUEE
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Division Algorithm - First Version
START: Place Dividend in REM
1. REM = REM - DIVR
REM ≥ 0
Restore
REM ≥ 0?
REM < 0
2b. REM = REM + DIVR
Shift QUOT left 1 bit; LSB=0
2a. Shift QUOT left 1 bit; LSB=1
2. Shift DIVR right 1 bit
33nd
Repitition?
No: <33 Repetitions
Yes: 33 Repetitions
DONE
CCUEE
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Divide 1st Version - Observations

We only subtract 32 bits in each iteration


Idea: Instead of shifting divisor to right,
shift remainder to left
First step cannot produce a 1 in quotient bit


CCUEE
Switch order to shift first, then subtract
Save 1 iteration
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Divide Hardware - 2nd Version



Divisor Holds Still
Dividend/Remainder Shifts Left
End Result: Remainder in upper half of register
DIVR (32 bits)
QUOT
LSB
(32 bits) Shift L
32-bit ALU
ADD/
SUB
Control
REM
Shift L
(64 bits)
Write
Sign bit (REM<0)
CCUEE
Computer Organization
55
Divide Hardware - 3rd Version

Combine quotient with remainder register
DIVR (32 bits)
32-bit ALU
ADD/
SUB
Control
REM
(64 bits)
Shift L
LSB
Write
Shift R
Sign bit (REM<0)
CCUEE
Computer Organization
56
Divide Algorithm - 3rd Version
START: Place Dividend in REM
1. Shift REM left 1 bit
2. LHREM = LHREM - DIVR
REM ≥ 0
REM ≥ 0?
REM < 0
3b. LHREM = LHREM + DIVR
Shift REM left 1 bit; LSB=0
3a.. Shift REM left 1 bit; LSB=1
32nd
Repitition?
No: <32 Repetitions
Yes: 32 Repetitions
DONE (shift LH right 1 bit)
CCUEE
Computer Organization
57
Dividing Signed Numbers



Check sign of divisor, dividend
Negate quotient if signs of operands are opposite
Make remainder sign match dividend (if nonzero)
CCUEE
Computer Organization
58
MIPS Divide Instructions

Divide Instructions



Results in Lo, Hi registers



Hi: remainder
Lo: quotient
Divide pseudoinstructions



div $s2, $s3
divu $s2, $s3
div $s3, $s2, $s1
divu $s3, $s2, $s1
# $s3 = $s2 / $s1
Software must check for overflow, divide-by-zero
CCUEE
Computer Organization
59
Summary - Multiplication and Division

Multiplication



Sequential multipliers - efficient but slow
Combinational multipliers - fast but expensive
Division is more complex and problematic


CCUEE
What about divide by zero?
Restore step needed to undo unwanted subtractions
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Floating Point - Motivation

Review: n-bit integer representations




Unsigned:
Signed Two’s Complement:
Biased (excess-b):
0 to 2n-1
- 2n-1 to 2n-1-1
-b to 2n-b
Problem: how do we represent:

Very large numbers

Very small numbers

Rational numbers
2/3
Irrational numbers
sqrt(2)
Transcendental numbers e, π


CCUEE
9,345,524,282,135,672,
2354
0.00000000000000005216,
2-100
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61
Fixed Point Representation


Idea: fixed-point numbers with fractions
Decimal point (binary point) marks start of fraction



Decimal: 1.2503 = 1  100 + 2  10-1 + 5  10-2 + 3  10-4
Binary: 1.0100001 = 1  20 + 1  2-2 + 1  2-7
Problems


CCUEE
Limited locations for “decimal point” (binary point”)
Won’t work for very small or very larger numbers
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Another Approach: Scientific Notation

Represent a number as a combination of



Mantissa (significand): Normalized number
AND
Exponent (base 10)
Example:
6.02  1023
Significand
(mantissa)
CCUEE
Exponent
Radix
(base)
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63
Floating Point

Key idea: adapt scientific notation to binary
Fixed-width binary number for significand
Fixed-width binary number for exponent (base 2)



Idea: represent a number as
1.xxxxxxxtwo  2yyyy
Leading ‘1’
(Implicit)

Significand
(mantissa)
Exponent
Radix
(2)
Important Points:


CCUEE
This is a tradeoff between precision and range
Arithmetic is approximate - error is inevitable!
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64
IEEE 754 Floating Point
Single precision (C/C++/Java float type)

S
E Exponent
1 bit
8 bits
F Significand
23 bits
Bias
Value N = (-1)S  1.F  2E-127
Double precision (C/C++/Java double type)

S
1 bit
E Exponent
F Significand
11 bits
20 bits
F Significand
(continued - 52 bits total)
32 bits
Value N = (-1)S  1.F  2E-1023
CCUEE
Computer Organization
Bias
65
Floating Point Examples

8.75ten = 1 X 23 + 1 X 2-1 + 1 X 2-2 = 1.00011 X 23

Single Precision:


Significand: 1.00011000…. (note leading 1 is implied)
Exponent: 3 + 127 = 130 = 10000010two
0 1 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
S

E Exponent
F Significand
Double Precision:


Significand: 1.00011000…
Exponent: 3 + 1023 = 1026 = 10000000010two
0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
S
E Exponent
F Significand
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
F Significand
CCUEE
(continued - 52 bits total)
Computer Organization
66
Floating Point Examples

-0.375ten = 1 X 2-2 + 1 X 2-3 = 1. 1 X 2-2

Single Precision:


Significand: 1.1000….
Exponent: -2 + 127 = 125 = 01111101two
1 0 1 1 1 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
S

E Exponent
F Significand
Double Precision:


Significand: 1.1000…
Exponent: -2 + 1023 = 1021 = 01111111101two
1 0 1 1 1 1 1 1 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
S
E Exponent
F Significand
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
F Significand
CCUEE
(continued - 52 bits total)
Computer Organization
67
Floating Point Examples

Q: What is the value of the following single-precision
word?
0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0
S



E Exponent
F Significand
Significand = 1 + 2-1 + 2-4 + 2-8 + 2-10 + 2-12
Exponent = 8 - 127 = -119
Final Result = (1 + 2-1 + 2-4 + 2-8 + 2-10 + 2-12) X 2-119
= 2.36 X 10-36
CCUEE
Computer Organization
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Special Values in IEEE Floating Point

0000000 exponent - reserved for


zero value (all bits zero)
“Denormalized numbers” - drop the “1.”



Used for “very small” numbers … “gradual underflow”
Smallest denormalized number (single precision):
0.00000000000000000000001 X 2-126 = 2-149
1111111 exponent


CCUEE
Infinity - 111111 exponent, zero significand
NaN (Not a Number) - 1111111 exponent, nonzero significand
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Floating Point Range and Precision


The tradeoff: range in exchange for uniformity
“Tiny” example: floating point with:


5 4
3 exponent bits
2 signficand bits
–
–10
0
2 1
S
s exp
–5
0
Denormalized
–0.8
–0.6
–0.4
–0.2
Denormalized
CCUEE
+5
Normalized
–0
–1
Graphic and Example Source:
R. Bryant and D. O’Halloran,
Computer Systems: A Programmer’s Perspective,
© Prentice Hall, 2002
+10
+
Infinity
+0
0
+0.2
Normalized
Computer Organization
+0.4
+0.6
+0.8
+1
Infinity
70
Visualizing Floating Point “Small” FP Representation

8-bit Floating Point Representation




the sign bit is in the most significant bit.
the next four bits are the exponent, with a bias of 7.
the last three bits are the frac
Same General Form as IEEE Format


normalized, denormalized
representation of 0, NaN, infinity)
7 6
s
0
3 2
exp
significand
Example Source:
R. Bryant and D. O’Halloran,
Computer Systems: A Programmer’s Perspective,
© Prentice Hall, 2002
CCUEE
Computer Organization
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Small FP - Values Related to Exponent
CCUEE
Exp
exp
E
2E
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
-6
-6
-5
-4
-3
-2
-1
0
+1
+2
+3
+4
+5
+6
+7
n/a
1/64
1/64
1/32
1/16
1/8
1/4
1/2
1
2
4
8
16
32
64
128
Computer Organization
(denorms)
(inf, Nan).
72
Small FP Example - Dynamic Range
s
0
Denormalized 0
numbers
0
…
0
0
0
0
…
0
Normalized 0
numbers
0
0
0
…
0
0
0
CCUEE
exp
0000
0000
0000
frac
000
001
010
E
-6
-6
-6
Value
0
1/8*1/64 = 1/512
2/8*1/64 = 2/512
0000
0000
0001
0001
110
111
000
001
-6
-6
-6
-6
6/8*1/64
7/8*1/64
8/8*1/64
9/8*1/64
=
=
=
=
6/512
7/512
8/512
9/512
0110
0110
0111
0111
0111
110
111
000
001
010
-1
-1
0
0
0
14/8*1/2
15/8*1/2
8/8*1
9/8*1
10/8*1
=
=
=
=
=
14/16
15/16
1
9/8
10/8
7
7
n/a
14/8*128 = 224
15/8*128 = 240
inf
1110 110
1110 111
1111 000
Computer Organization
closest to zero
largest denorm
smallest norm
closest to 1 below
closest to 1 above
largest norm
73
Learning from Tiny & Small FP

Non-uniform spacing of numbers




very small spacing for large negative exponents
very large spacing for large positive exponents
Exact representation: sums of powers of 2
Approximate representation: everything else
CCUEE
Computer Organization
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Summary: IEEE Floating Point Values
Single
precision
Double precision
Object Represented
Exponent
Significand
Exponent
Significand
0
0
0
0
0
0
nonzero
0
nonzero
+/- denormalized
number
1-254
anything
1-2046
anything
+/- floating-point
number
255
0
2047
0
+/0 infinity
255
nonzero
2047
nonzero
NaN (Not a Number)
Source: book p. 301
CCUEE
Computer Organization
75
IEEE Floating Point Interesting Numbers
Description
exp
frac
Zero
00…00 00…00
Smallest Pos. Denorm.
00…00 00…01
 Single  1.4 X 10–45
 Double  4.9 X 10–324
Largest Denormalized
00…00 11…11
 Single  1.18 X 10–38
 Double  2.2 X 10–308
Smallest Pos. Normalized 00…01 00…00
 Just larger than largest denormalized
One
01…11 00…00
Largest Normalized
11…10 11…11
 Single  3.4 X 1038
 Double  1.8 X 10308
CCUEE
Numeric Value
0.0
2– {23,52} X 2– {126,1022}
(1.0 – ) X 2– {126,1022}
1.0 X 2– {126,1022}
1.0
(2.0 – ) X 2{127,1023}
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Floating Point Addition (Fig. 3.16)
1. Align binary point to number with larger exponent
2. Add significands
3. Normalize result and adjust exponent
4. If overflow/underflow throw exception
5. Round result (go to 3 if normalization needed again)
A
1.11 X 20 1.11 X 20 1.75
+ B + 1.00 X 2-2
+ 0.01 X 20 0.25
10.00 X 20
(Normalize)
1.00 X 21 2.00
Hardware - Fig. 3.17, p. 201
CCUEE
Computer Organization
77
Floating Point Multiplication (Fig.
3.18)
1. Add 2 exponents together to get new exponent (subtract
127 to get proper biased value)
2. Multiply significands
3. Normalize result if necessary (shift right) & adjust
exponent
4. If overflow/underflow throw exception
5. Round result (go to 3 if normalization needed again)
6. Set sign of result using sign of X, Y
CCUEE
Computer Organization
78
MIPS Floating Point Instructions

Organized as a coprocessor

Separate registers $f0-$f31

Separate operations
Separate data transfer (to same memory)


Basic operations




CCUEE
add.s - single
sub.s - single
mul.s - single
div.s - single
add.d - double
sub.d - double
mul.d - double
div.d - double
Computer Organization
79
MIPS Floating Point Instructions
(cont’d)

Data transfer



lwc1, swcl (l.s, s.s) - load/store float
to fp reg
l.d, s.d - load/store double to fp reg pair
Testing / branching



CCUEE
c.lt.s, c.lt.d, c.eq.s, c.eq.d, …
compare and set condition bit if true
bclt - branch if condition true
bclf - branch if condition false
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Rounding

Extra bits allow rounding after computation




Guard Digit (may shift into number during normalization)
Round digit - used to round when guard bit shifted during
normalization
Sticky bit - used when there are 1’s to the right of the round digit
e.g., “0.010000001” (round to nearest even)
IEEE 754 supports four rounding modes




CCUEE
Always round up
Always round down
Truncate
Round to nearest even (most common)
Computer Organization
81
Limitations on Floating-Point Math




Most numbers are approximate
Roundoff error is inevitable
Range (and accuracy) vary depending on exponent
“Normal” math properties not guaranteed:

Inverse
Associative

Distributive


(1/r)*r
(A+B) +
(A*B) *
(A+B) *
≠
C
C
C
1
≠ A + (B+C)
≠ A * (B*C)
≠ A*B + B*C
Scientific calculations require error management take a
numerical analysis for more info
CCUEE
Computer Organization
82
IEEE Floating Point - Special Properties

Floating Point 0 same as Integer 0


All bits = 0
Can (Almost) Use Unsigned Integer Comparison

A > B if:





This is equivalent to
unsigned comparision!
But, must first compare sign bits
Must consider -0 == 0
NaNs problematic


CCUEE
A.EXP > B.EXP or
A.EXP=B.EXP and A.SIG > B.SIG
Will be greater than any other values
What should comparison yield?
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Summary - Chapter 3

Important Topics







Signed & Unsigned Numbers (3.2)
Addition and Subtraction (3.3)
Carry Lookahead (B.6)
Constructing an ALU (B.5)
Multiplication and Division (3.4, 4.5)
Floating Point (3.6)
Coming Up:

CCUEE
Performance (Chapter 4)
Computer Organization
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