Transcript EE 335 Computer Architecture

CMPE 325 Computer
Architecture II
Cem Ergün
Eastern Mediterranean University
Multiplication & Division Algorithms
Binary Multiplication
• At each step we multiply the multiplicand
by a single digit from the multiplier.
– In binary, we multiply by either 1 or 0 (much
simpler than decimal).
• Keep a running sum instead of storing and
adding all the partial products at the end.
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Multiplication & Division Algorithms
Multiplication
• Long-hand multiplication (12 × 9 = 108)
1 1 0 0 = 12ten
× 1 0 0 1 = 9ten
----------------------1 1 0 0
0 0 0 0 0
0 0 0 0 0 0
+ 1 1 0 0 0 0 0
----------------------1 1 0 1 1 0 0 = 108ten
(n bit Multiplicand)
(m bit Multiplier)
(n + m bit Product)
• The result is a number that is n + m - 1 bits long
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Multiplication & Division Algorithms
Implementing Multiplication
• Several different ways to implement
• Things to note about previous method
– At each step we either copied or set the value to 0
– LSBs of the product don’t change once computed
 Can form product by shifting and adding
• Solution #1
– Shift multiplicand left at each step (same as adding 0’s)
– Shift multiplier right so we can always consider the 0’th bit
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Multiplication & Division Algorithms
Solution #1
• Multiplication without sign (12 × 9 = 108)
1 1 0 0 = 12ten
× 1 0 0 1 = 9ten
----------------------1 1 0 0
0 0 0 0 0
0 0 0 0 0 0
+ 1 1 0 0 0 0 0
----------------------1 1 0 1 1 0 0 = 108ten
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(n bit Multiplicand)
(m bit Multiplier)
Multiplicand
0 0
1 0
1 0
1
Multiplier
1 0 0 1
Product
0 0
1 0
1 0
1
0 1
0 0 0
0
1 0
1 0 0
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Multiplication & Division Algorithms
Start
Solution #1:
Operations
Multiplier0 = 1
1. Test
Multiplier0
Multiplier0 = 0
1a. Add multiplicand to product and
place the result in Product register
2. Shift the Multiplicand register left 1 bit
3. Shift the Multiplier register right 1 bit
32nd repetition?
No: < 32 repetitions
Yes: 32 repetitions
Done
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Multiplication & Division Algorithms
Solution #1: Example
Iter
Step
Multiplier
Multiplicand
Product
0
Initial Values
1001
0000 1100
0000 0000
1
Multiplier[0]=1  Prod+Mcand
1001
0000 1100
0000 1100
Shift multiplicand left
1001
0001 1000
0000 1100
Shift multiplier right
0100
0001 1000
0000 1100
Multiplier[0]=0  Do nothing
0100
0001 1000
0000 1100
Shift multiplicand left
0100
0011 0000
0000 1100
Shift multiplier right
0010
0011 0000
0000 1100
Multiplier[0]=0  Do nothing
0010
0011 0000
0000 1100
Shift multiplicand left
0010
0110 0000
0000 1100
Shift multiplier right
0001
0110 0000
0000 1100
Multiplier[0]=1  Prod+Mcand
0001
0110 0000
0110 1100
Shift multiplicand left
0001
1100 0000
0110 1100
Shift multiplier right
0000
1100 0000
0110 1100
2
3
4
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Multiplication & Division Algorithms
Solution #1: Hardware
Shift Left
Multiplicand
64 bits
64-bit ALU
Add
Multiplier
Shift Right
32 bits
Product
Write
Control
64 bits
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Multiplication & Division Algorithms
Adjustments to Algorithm 1
• One big problem with the
algorithm/implementation shown:
– need a 64 bit ALU (adder).
– Half of the multiplicand bits are always 0
• Either high or low bits are 0, even as shifted
– LSB of product never changes once set
– Half of the 64 bit adder is therefore wasted
• We can fix this by:
– Leaving the multiplicand alone (don’t shift).
– Instead of shifting multiplicand left, shift the
product right
– Add multiplicand to left half of running sum.
– Adder only needs to be 32 bits wide
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Multiplication & Division Algorithms
Start
Solution #2:
Adjusted Algorithm
Multiplier0 = 1
1. Test
Multiplier0
Multiplier0 = 0
1a. Add multiplicand to the left half of
the product and place the result in
the left half of the Product register
Revised Addition
2. Shift the Product register right 1 bit
Shift partial sum
instead of multiplicand
3. Shift the Multiplier register right 1 bit
32nd repetition?
No: < 32 repetitions
Yes: 32 repetitions
Done
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Multiplication & Division Algorithms
Solution #2: Example
Iter
Step
Multiplier Multiplicand
Product
0
Initial Values
1001
1100
0000 0000
1
Multiplier[0]=1  Prod+Mcand
1001
1100
1100 0000
Shift product right
1001
1100
0110 0000
Shift multiplier right
0100
1100
0110 0000
Multiplier[0]=0  Do nothing
0100
1100
0110 0000
Shift product right
0100
1100
0011 0000
Shift multiplier right
0010
1100
0011 0000
Multiplier[0]=0  Do nothing
0010
1100
0011 0000
Shift product right
0010
1100
0001 1000
Shift multiplier right
0001
1100
0001 1000
Multiplier[0]=1  Prod+Mcand
0001
1100
1101 1000
Shift product right
0001
1100
0110 1100
Shift multiplier right
0000
1100
0110 1100
2
3
4
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Multiplication & Division Algorithms
Solution #2: Hardware
Multiplicand
32 bits
32-bit ALU
Add
Multiplier
Shift Right
32 bits
Shift Right
Product
64 bits
Control
Write
Upper 32 bits
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Multiplication & Division Algorithms
Issues and Alternative
• In the implementation of the adjusted algorithm it is possible to save
space by putting the multiplier in the rightmost 32 bits of the product
register.
– If you notice, half of the product register is useless at the
beginning
– At the end, the multiplier register becomes useless
• Solution #3 The algorithm is the same, but steps 2 and 3 are done at
the same time.
– Remove the multiplier register
– Place the multiplier value in the lower half of the product register
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Multiplication & Division Algorithms
Solution #3:
Operations
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Multiplication & Division Algorithms
Solution #3: Example
Iter
Multiplicand
Product
0
Initial Values
1100
0000 1001
1
Product[0]=1  Prod+Mcand
1100
1100 1001
Shift product right
1100
0110 0100
Product[0]=0  Do nothing
1100
0110 0100
Shift product right
1100
0011 0010
Product[0]=0  Do nothing
1100
0011 0010
Shift product right
1100
0001 1001
Product[0]=1  Prod+Mcand
1100
1101 1001
Shift product right
1100
0110 1100
2
3
4
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Step
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Multiplication & Division Algorithms
Solution #3: Hardware
Multiplicand
32 bits
32-bit ALU
Add
Shift Right
Product
Write
64 bits
Upper 32 bits
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Control
Multiplier
LSB
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Multiplication & Division Algorithms
Signed Multiplication
• Previous algorithms work for unsigned.
• We could:
– convert both multiplier and multiplicand to positive
before starting, but remember the signs.
– adjust the product to have the right sign (might need
to negate the product).
– Set the sign bit to make the number negative if the
multiplicand and multiplier disagree in sign
•
•
•
•
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Positive × Positive = Positive
Negative × Negative = Positive
Positive × Negative = Negative
Negative × Positive = Negative
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Multiplication & Division Algorithms
Supporting Signed Integers
• We can adjust the previous algorithm to
work with signed integers
• make sure each shift is an arithmetic shift
– right shift – extend the sign bit (keep the MS
bit the same instead of shifting in a 0).
• Since addition works for signed numbers,
the multiply algorithm will now work for
signed numbers.
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Multiplication & Division Algorithms
1110 x 0011 (-2 x 3)
Step
1a
2,3
1a
2,3
1
2,3
1
2,3
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Multiplicand
1110
1110
Product
00000011
11100011
1110
11110001
11010001
1110
11101000
11101000
1110
11110100
11110100
11111010
multiplier is
rightmost 4 bits
1st partial product
in left 4 bits
Shift Right
Result is 2s complement
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Multiplication & Division Algorithms
Signed Third Multiplication Algorithm
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Multiplication & Division Algorithms
Improving the speed with
Combinational Array Multiplier
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Multiplication & Division Algorithms
Combinational Array Multiplier
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Multiplication & Division Algorithms
Combinational Array Multiplier
3 bit Example
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Multiplication & Division Algorithms
Booth’s Algorithm
• Requires that we can do an addition or a
subtraction each iteration (not always an
addition).
• Uses the following property
– the value of any consecutive string of 1s in a
binary number can be computed with one
subtraction.
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Multiplication & Division Algorithms
A different way to compute
integer values
0110
23
23-21
(8-2=6)
21
0011111000 28-23
28
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(256-8 = 248)
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Multiplication & Division Algorithms
A little more complex example
010011010
28-27 + 25-23 + 22-21
28 27
22 21
25
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256-128 + 32-8 + 4-2
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Multiplication & Division Algorithms
An overview of Booth’s
Algorithm
• When doing multiplication, strings of 0s in the
multiplier require only shifting (no addition).
• When doing multiplication, strings of 1s in the
multiplier require operation and shifting.
• We need to add or subtract only at positions in
the multiplier where there is a transition from a 0
to a 1, or from a 1 to a 0.
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Multiplication & Division Algorithms
Booth Explanation
• Booth also works for negative numbers
• Booth Algorithm
– Add additional bit to the right of product
– Use right two bits of product to determine action
– Use arithmetic right shift
End of
string 0
(
)
Beginning
0 1 1 1 1 0 0 of string
Middle of string
Current Bit Right Bit
0
0
0
1
1
0
1
1
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Explanation
Middle of string of 0s
End of string of 1s
Beginning of string of 1s
Middle of string of 1s
Action
Do nothing
Add multiplicand
Subtract multiplicand
Do nothing
Multiplication & Division Algorithms
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Shifting
• The second step of
the algorithm is the
same as before: shift
the product/multiplier
right one bit.
– Arithmetic shift
needed for signed
arithmetic.
– The bit shifted off the
right is saved and
used by the next step
1 (which looks at 2
bits).
Booth’s Algorithm
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Multiplication & Division Algorithms
Booth Example
• Consider the same example, but think of it as a signed
multiplication (-4×-7=28)
Iter
Multiplicand
Product
0
Initial Values
1100
0000 1001 0
1
Product=10  Prod-Mcand
1100
0100 1001 0
Shift product right
1100
0010 0100 1
Product=01  Prod+Mcand
1100
1110 0100 1
Shift product right
1100
1111 0010 0
Product=00  Do nothing
1100
1111 0010 0
Shift product right
1100
1111 1001 0
Product=10  Prod-Mcand
1100
0011 1001 0
Shift product right
1100
0001 1100 1
2
3
4
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Step
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Multiplication & Division Algorithms
Multiply in MIPS
• Product stored in two 32 bit registers called Hi and Low
mult $s0, $s1
multu $s0, $s1
# $s0 * $s1 high/low
# $s0 * $s1 unsigned
• Results are moved from Hi/Low
mfhi $t0
mflo $t0
# $t0 = Hi
# $t0 = Low
• Pseudoinstruction
mul $t0, $s0, $s1
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# $t0 = $s0 * $s1
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Multiplication & Division Algorithms
Divide
• Long-hand division (108 ÷ 12 = 9)
N+
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1 0 0 1
+--------------1 1 0 0 | 1 1 0 1 1 0 0
- 1 1 0 0
--------0 0 1 1
- 0 0 0 0
--------0 1 1 0
- 0 0 0 0
--------1 1 0 0
- 1 1 0 0
--------1 Steps
0 0 0 0
(n bit Quotient)
+----------------(Divisor) | (Dividend)
(Remainder)
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Multiplication & Division Algorithms
Divide Solution #1
rem = rem - div
• Solution #1
– Start with quotient = 0,
remainder = dividend, and
divisor’s top bits set
– On each iteration set
remainder to be remainder –
divisor
– If large enough (remainder 
0), then shift quotient left and
set rightmost to 1
– If not large enough (remainder
< 0), then set remainder to
remainder + divisor (restore)
– Shift divisor right
– Continue for n+1 (33) iterations
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if rem < 0 then
// divisor too big
rem = rem + div
quo <<= 1
LSB(quo) = 0
else
// can divide
quo <<= 1
LSB(quo) = 1
fi
div >>= 1
repeat unless done
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Multiplication & Division Algorithms
Start
Divide
Solution #1
1. Subtract the Divisor register from the
Remainder register and place the
result in the Remainder register
Remainder –> 0
Test Remainder
2a. Shift the Quotient register to the left,
setting the new rightmost bit to 1
Remainder < 0
2b. Restore the original value by adding
the Divisor register to the Remainder
register and place the sum in the
Remainder register. Also shift the
Quotient register to the left, setting the
new least significant bit to 0
3. Shift the Divisor register right 1 bit
33rd repetition?
No: < 33 repetitions
Yes: 33 repetitions
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Done
Multiplication & Division Algorithms
34
Solution #1: Hardware
Shift Right
Divisor
64 bits
Quotient
64-bit ALU
Shift Left
32 bits
Remainder
Write
Control
64 bits
MSB
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Multiplication & Division Algorithms
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Multiplication & Division Algorithms
00000111 / 0010
Step
1
2b
3
1
2b
3
1
2a
3
1
2a
3
1
2a
3
Quotient
0000
Divisor
00100000
0000
Remainder
00000111
11100111
00000111
00010000
initial values
after subtraction
after restore
11110111
00000111
0000
00001000
shift right
11111111
00000111
0000
00000100
00000011
0001
00000010
00000001
final remainder
0011
00000001
final quotient
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Multiplication & Division Algorithms
Division Example: 1001001/0101
Initial Values (Divisor in LHS)
•1a. Rem. <-- Rem-Divisor
•1b. Rem.<0, Add Div., LSh Q, Q0=0; RSh Div.
•2a. Rem. <-- Rem-Divisor
•2b. Rem>=0, LSh Q, Q0=1; RSh Div.
•3a. Rem. <-- Rem-Divisor
•3b. Rem>=0, LSh Q, Q0=1; RSh Div.
•4a. Rem. <-- Rem-Divisor
•4b. Rem>=0, LSh Q, Q0=1; RSh Div.
•5a. Rem. <-- Rem-Divisor
•5b. Rem<0, Add Div., LSh Q, Q0=0; RSh Div.
Divisor
ShRight
64 bit
64-bit
Remainder
Write
64 bit
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ShLeft
Quotient
32 bit
Control
Quotient Divisor
Remainder
xxxx
xxxx
01010000 01001001
01010000 11111001
xxx0
xxx0
xx01
xx01
00101000 01001001
00101000 00100001
2
00010100 00100001
00010100 00001101
x011
x011
00001010 00001101
00001010 00000011
0111
0111
00000101 00000011
00000101 11111110
1110
00000010 00000011
3
1001001/0101 = 1110 rem 0011
73/5 = 14 rem 3
N+1 Steps, but first step cannot produce a 1.
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Multiplication & Division Algorithms
1
4
5
Issues and Alternative
• Just as before
– Half of the divisor bits are always 0
• Either high or low bits are 0, even as shifted
– Half of the 64 bit adder is therefore wasted
• Solution #2
– Instead of shifting divisor right, shift the remainder left
– Adder only needs to be 32 bits wide
– Can also remove iteration by switching order to shift and then
subtract
– Remainder is in left half of register
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Multiplication & Division Algorithms
Solution #2: Hardware
Divisor
32 bits
Quotient
32-bit ALU
Shift Left
32 bits
Shift Left
Remainder
Control
Write
64 bits
MSB
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Multiplication & Division Algorithms
Improved Divider: 1001001/0101
Initial Values
•0. LSh Rem
•1a. Rem. <-- Rem-Divisor
•1b. Rem>=0, LSh Q, Q0=1; LSh Rem.
•2a. Rem. <-- Rem-Divisor
•2b. Rem>=0, LSh Q, Q0=1; LSh Rem.
•3a. Rem. <-- Rem-Divisor
•3b. Rem>=0, LSh Q, Q0=1; LSh Rem.
•4a. Rem. <-- Rem-Divisor
•4b. Rem<0, Add Div., LSh Q, Q0=0
Divisor
32 bit
ShLeft
32-bit
LH Rem.
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RH Rem.
64 bit
Write
ShLeft
Control
Quotient
32 bit
Quotient Divisor
Remainder
xxxx
xxxx
0101
0101
01001001
1001001x
xxxx
0101
xxx1
xxx1
xx11
xx11
0101
0101
0101
0101
x111
x111
0101
0101
0011xxxx
1110xxxx
1110
0101
0011xxxx
-
0100001x
100001xx
001101xx
2
01101xxx
00011xxx
-
3
1001001/0101 = 1110 rem 0011
73/5 = 14 rem 3
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Multiplication & Division Algorithms
1
4
Issues and Alternative
• Just as before, half of the remainder register is useless at the
beginning
• At the end, the quotient register becomes useless
• Solution #3
– Remove the quotient register
– Place the quotient in the lower half of the remainder register
– Need to unshift in the last step to account for off-by-one
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Multiplication & Division Algorithms
Further Modifications
Solution#3
• Same space savings as with multiplication:
– use right ½ of remainder register to hold the
quotient.
Divisor
32 bits
quotient
32-bit ALU
Shift right
Remainder Shift left
Write
Control
test
64 bits
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Multiplication & Division Algorithms
Start
Divide Solution #3
1. Shift the Remainder register left 1 bit
rem <<= 1
rem -= (div >> 32)
if rem < 0 then
2. Subtract the Divisor register from the
left half of the Remainder register and
place the result in the left half of the
Remainder register
rem += (div >> 32)
rem <<= 1
Remainder >
– 0
Test Remainder
Remainder < 0
LSB(rem) = 0
else
3a. Shift the Remainder register to the
left, setting the new rightmost bit to 1
rem <<= 1
3b. Restore the original value by adding
the Divisor register to the left half of the
Remainder register and place the sum
in the left half of the Remainder register.
Also shift the Remainder register to the
left, setting the new rightmost bit to 0
LSB(rem) = 1
fi
repeat unless done
32nd repetition?
No: < 32 repetitions
Yes: 32 repetitions
Correct remainder
Done. Shift left half of Remainder right 1 bit
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Multiplication & Division Algorithms
Solution #3: Example
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Multiplication & Division Algorithms
Improved Improved Divider: 1001001/0101
Initial Values
•0. LSh Rem-Quo.
•1a. Rem <-- Rem-Divisor
•1b. Rem>=0, LSh Rem-Quo, Q0=1
•2a. Rem. <-- Rem-Divisor
•2b. Rem>=0, LSh Rem-Quo, Q0=1
•3a. Rem. <-- Rem-Divisor
•3b. Rem>=0, LSh Rem-Quo, Q0=1
•4a. Rem. <-- Rem-Divisor
•4b. Rem<0, Add Div., LSh Rem-Quo, Q0=0
Divisor
32 bit
•Final: RSh Rem 1
32-bit
LH Rem.
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Rem-Quot.
64 bit
Write
ShLeft
Control
Divisor
Remainder-Quotient
0101
0101
01001001
10010010
0101
0101
0101
0101
0101
-
01000010
1
10000101
00110101
2
01101011
00011011
-
3
0101
0101
00110111
11100111
0101
0101
01101110
00111110
4
1001001/0101 = 1110 rem 0011
73/5 = 14 rem 3
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Multiplication & Division Algorithms
Signed Division
• Same process as naïve integer multiply
– Make divisor and dividend positive
– Negate quotient if signs of divisor and dividend disagree
• Set sign of remainder
– Dividend = Quotient × Divisor + Remainder
– Sign should match dividend
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Multiplication & Division Algorithms
Divide in MIPS
• Quotient/Remainder stored in two 32 bit registers called
Hi and Low
div $s0, $s1
divu $s0, $s1
# $s0 / $s1 high/low
# $s0 / $s1 unsigned
• Results are moved from Hi/Low
mfhi $t0
mflo $t0
# $t0 = Hi
# $t0 = Low
div $s0,$s1
Lo = $s0/$s1 (integer)
Hi = $s0 % $s1
• Pseudoinstructions
div $t0, $s0, $s1
rem $t0, $s0, $s1
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# $t0 = $s0 / $s1
# $t0 = $s0 % $s1
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Multiplication & Division Algorithms