Transcript BDLC - EDN China

BYTE DATA LINK
CONTROLLER
(BDLC )
HCS12 Technical Training, Rev 2.0
Module 11- BDLC, Slide 1
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
ATD
1
ATD
0
12K
SRAM
256K
FLASEEPROM
SCI
1
SCI
1
Internal Bus
SPI 2 SPI 1
or
or
PWM
PWM
PWM
SPI 0
8
CH CH
CHAN
4-7
0-3
msCAN
4
or
IIC
msCAN
3
msCAN
2
BKP INT
HCS12 CPU
msCAN
1
BDLC
or
msCAN
0
MMI
SIM
CM BDM
MEBI
PIM PLL
PIT
4K
BYTES
EEPROM
ECT
8
CHAN
HCS12 Technical Training, Rev 2.0
Module 11- BDLC, Slide 2
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
BDLC
CONTROLLER
FEATURES:
• SAE J1850 Compatible
• 10.4Kbps VPW bit format
• Digital noise filter
• Collision detection
• Hardware CRC generation & checking
• Receive and Transmit Block mode supported
• Supports 4X receive mode (41.6 Kbps)
• Digital loopback mode
• In-frame Response (IFR) Types 0, 1, 2, and
3 supported
• Power-Saving Stop and Wait modes with Automatic
Wakeup on Network Activity
• Interrupt Generation with Vector Lookup Table
HCS12 Technical Training, Rev 2.0
Module 11- BDLC, Slide 3
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
BDLC Block Diagram
To J1850 Bus
Physical Interface: performs wave shaping, driving and digitizing of data
MUX Interface: provides link between the BDLC digital section and the analog Physical Interface
Protocol Handler: responsible for encoding and decoding of data bits and special message symbols
Rx/Tx Buffers: provide storage for data received and transmitted onto the J1850 bus
CPU Interface: contains software addressable registers and provides link between CPU and Buffers
To CPU
HCS12 Technical Training, Rev 2.0
Module 11- BDLC, Slide 4
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
OPERATING MODES
Power Off
Vdd > Vdd(Min) and any MCU reset source asserted
Vdd < Vdd(Min)
Reset
Any MCU reset source asserted
(from any mode)
(COP,CM, RESET, POR)
Network Activity or other MCU wake-up
No MCU reset source asserted
Network activity or other MCU wake-up
Run
(WAIT instruction and WCM =0)
BDLC Stop
STOP Instruction or (WAIT
instruction and WCM =1)
BDLC Wait
HCS12 Technical Training, Rev 2.0
Module 11- BDLC, Slide 5
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
BDLC BLOCK DIAGRAM
To J1850 Bus
Physical Interface: performs wave shaping, driving and digitizing of data
MUX Interface: provides link between the BDLC digital section and the analog Physical Interface
Protocol Handler: responsible for encoding and decoding of data bits and special message symbols
Rx/Tx Buffers: provide storage for data received and transmitted onto the J1850 bus
CPU Interface: contains software addressable registers and provides link between CPU and Buffers
To CPU
HCS12 Technical Training, Rev 2.0
Module 11- BDLC, Slide 6
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
BDLC CPU Interface
CPU Interface: contains software addressable registers
and provides link between HCS12 CPU and Buffers
Address Offset
BDLC Control Register 1 (DLCBCR1)
BDLC State Vector Register (DLCBSVR)
$0000
$0001
BDLC Control Register 2 (DLCBCR2)
$0002
BDR Protocol handler (BDR)
$0003
BDLC Analog Roundtrip Delay (DLCBARD)
$0004
BDLC Rate Select Register (DLCBRSR)
$0005
DLCBDLC Port Register (DLCSCR)
$006
BDLC Port Direction (DLCBSTAT)
$0007
User Registers
HCS12 Technical Training, Rev 2.0
Module 11- BDLC, Slide 7
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
BDLC Control Registers
DLCBCR1 - BDLC Control Register 1
Address Offset
$0000
–
Ignore Message (IMSG)
• Disables receiver until new Start of Frame (SOF) is detected
• Cleared automatically by reception of SOF symbol or a BREAK symbol
It then generates interrupt requests and will allow changes to the status register to occur
• All BDLC interrupt requests will be masked when this bit is set
1 = Disable Receiver
0 = Enable Receiver
–
Clock Select (CLKS)
• Selects BDLC Nominal Frequency (fbdlc)
1 = Binary frequency (1.048576 MHz) is used for fbdlc
0 = Integer frequency (1 MHZ) is used for fbdlc
–
•
Wait Clock Module (WCM)
– Determines operation of BDLC during CPU Wait mode
1 = Stop BDLC internal clocks during CPU wait mode
0 = Wait BDLC internal clocks during CPU wait mode
Rate Select (R1, R0)
• Determines the amount by which the frequency of the MCU system clock signal (fTCLKS) is divided to form the MUX
Interface clock (fbdlc)
³ Defines the basic timing resolution of the MUX Interface
–
Interrupt Enable (IE)
1 = Enable Interrupt requests from BDLC
0 = Disable Interrupt requests from BDLC
HCS12 Technical Training, Rev 2.0
Module 11- BDLC, Slide 8
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
BDLC Rate Selection
DLCBRSR - BDLC Rate Select Register
BDLC Rate Selection for Binary Frequencies
Address Offset
$0005
BDLC Rate Selection for Integer Frequencies
HCS12 Technical Training, Rev 2.0
Module 11- BDLC, Slide 9
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
BDLC Control Registers
DLCBCR2 - BDLC Control Register 2
Address Offset
$0002
–
–
State Machine Reset (SMRST)
1 = Arms the state Machine but does not reset BDLC
0 = Clearing SMRST after it has been set, causes BDLC to reset
Digital Loopback Mode (DLOOP)
• Determines the source to which RXPD is connected and
can be used to isolate bus fault conditions
1 = RxPD is connected to TxPD, BDLC is now in Digital
Loopback Mode
0 = RxPD is connected to RxPA, BDLC is taken out of Digital
Loopback Mode
– Receive 4X Enable (RX4XE)
• Determines if the BDLC operates at normal transmit
and receive speed (10.4 kbps) or receive only at 41.6 kbps
1 = BDLC is put in 4X receive only operation
0 = BDLC transmits and receives at 10.4 kbps
• Normalized Bit Format Select(NBFS)
– Control the format of the Normalization Bit (NB)
1 = NB that is received or transmitted is a
‘0’ when the response part of IN-Frame
Response (IFR) ends with a CRC byte.
0 = NB that is received or transmitted is a
‘1’ when the response part of IN-Frame
Response (IFR) ends with a CRC byte.
• Transmit End of Data (TEOD)
– Set by programmer to indicate the end of a
message being sent by the BDLC
1 = Transmit EOD symbol
0 = TEOD bit will be automatically cleared at
the rising edge of the first CRC bit that is
sent , or if an error is detected
Rx4x4 Defines the basic timing resolution of the MUX Interface
HCS12 Technical Training, Rev 2.0
Module 11- BDLC, Slide 10
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
BDLC Frame Format
SOF - Start of Frame Symbol
A message Frame always begins with a SOF symbol
Data – In Message Data Bytes
The data bytes contained in the message include the message
priority/type, message I.D. byte, and any actual data being transmitted
to the receiving node.
CRC – Cyclical Redundancy
This byte is used by the receiver(s) of each message to determine if any
errors have occurred during the transmission of the message.
EOD – End of Data Symbol
The EOD symbol is a long passive period on the J1850 bus used to
signify to any recipients of a message that the transmission by the
originator has completed.
EOF – End of Frame Symbol
This symbol is a passive period on the J1850 bus,
longer than an EOD symbol, which signifies the end
of a message. Since an EOF symbol is longer than
an EOD symbol, if no response is transmitted after an
EOD symbol, it becomes an EOF, and the message is
assumed to be completed.The EOF flag is set upon
receiving the EOF symbol.
IFS – Inter-Frame Separation Symbol
The IFS symbol is a passive period on the J1850 bus which
allows proper synchronization between nodes during continuous
message transmission. The IFS symbol is transmitted by a node
following the completion of the EOF period.
IFR – In Frame Response Bytes
The IFR section of the J1850 message format is optional. Users desiring
further definition of in-frame response should review the “SAE J1850
HCS12 Technical Training, Rev 2.0
Module 11- BDLC, Slide 11
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
Transmit In-Frame Response Control
(TSIFR, TMIFR1, TMIFR0)
•
•
Control the type of In-Frame Response being sent
Programmer should not set more than one of these control bits to a one at any given time
– If more than one of these three control bits are set to one, the priority encoding logic will
force these register bits to a known value
Transmit In-Frame Response Control Bit Priority Encoding
WRITE
TSIFR1
WRITE
TMIFR1
WRITE
TMIFR0
ACTUAL
TSIFR
ACTUAL
TMIFR1
ACTUAL
TMIFR0
0
0
0
0
0
0
1
X
X
1
0
0
0
1
X
0
1
0
0
0
1
0
0
1
Types of In-Frame
Response
HCS12 Technical Training, Rev 2.0
Module 11- BDLC, Slide 12
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
BDLC State Vector Register
DLCBDLC - State Vector Register
Address Offset
$0001
•
•
Decreases CPU overhead associated with servicing interrupts while under operation of a MUX protocol
It provides a index offset that is directly related to the BDLC’s current state, which can be used with a user
supplied jump table to rapidly enter an interrupt service routine
•
•
Eliminates the need for the user to maintain a duplicate state machine in software.
I0, I1, I2, I3 - indicate the source off the interrupt request that is currently pending
BSVR
$00
$04
$08
$0C
$10
$14
$18
$1C
$20
I3
0
0
0
0
0
0
0
0
1
I2
0
0
0
0
1
1
1
1
0
I1
0
0
1
1
0
0
1
1
0
I0
0
1
0
1
0
1
0
1
0
Interrupt Source
No Interrupt Pending
Received EOF
Received IFR byte (RXIFR)
Rx Data register full (RDRF)
Tx data register empty (TDRE)
Loss of arbitration
CRC error
Symbol invalid or out of range
Wakeup
HCS12 Technical Training, Rev 2.0
Module 11- BDLC, Slide 13
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
Priority
0(lowest)
1
2
3
4
5
6
7
8(highest)
BDLC Data Register
Address Offset
$0003
DLCBDR - BDLC Data Register
•
•
•
BDLC Data Register
Used to pass the data to be transmitted to the J1850 bus from the CPU to the BDLC
Used to pass data received from the J1850 bus to the CPU
DLCBDR is double buffered via a transmit shadow register and receive shadow register
TRANSMITTER:
RECEIVER:
DATA IN
DATA IN
Rx Shift Register
Transmit Shadow Register
Receive Shadow Register
Tx Shift Register
DATA OUT
DATA OUT
• TDRE Flag sets each time new data is
transferred from the Transmit Shadow Register
to the transmit Tx shift register.
• RDRF Flag sets each time new data
is transferred from the Rx shift register
to the Receive Shadow Register.
HCS12 Technical Training, Rev 2.0
Module 11- BDLC, Slide 14
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
BDLC Analog Round Trip Register
DLCBARD - BDLC Round Trip Delay Register
Address Offset
$0004
BO[3:0] Bit Encoding
BARD Offset
Expected Delay
[B3:B0]
(us)
0000
9
0001
10
1110
23
1111
24
RxPOL - Receive Pin Polarity
0 = Select Inverted Polarity
1 = Select Normal Polarity
DLCSCR - BDLC Control Register
Address Offset
$0006
BDLCE - BDLC Enable
0 = BDLC Pins are set for GPI/O
1 = BDLC Pins are set for BDLC Function
DLCBSTAT - BDLC Status Register
$0007
IDLE
1 = BDLC received IFS (No Data being transmitted or received)
0 = BDLC is either transmitting or receiving
HCS12 Technical Training, Rev 2.0
Module 11- BDLC, Slide 15
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
BDLC BLOCK DIAGRAM
To J1850 Bus
Physical Interface: performs wave shaping, driving and digitizing of data
MUX Interface: provides link between the BDLC digital section and the analog Physical Interface
Protocol Handler: responsible for encoding and decoding of data bits and special message symbols
Rx/Tx Buffers: provide storage for data received and transmitted onto the J1850 bus
CPU Interface: contains software addressable registers and provides link between CPU and Buffers
To CPU
BDLC Protocol Handler: Responsible for framing, collision detection,
arbitration, CRC generation/checking, and error detection. It conforms to
SAE J1850 - Class B Data Communications Network Interface.
HCS12 Technical Training, Rev 2.0
Module 11- BDLC, Slide 16
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
PROTOCOL ARCHITECTURE
To Physical Interface
TxP
RxP
DLOOP from BCR2
loopback control
Loopback
Multiplexer
Control
TxP
RxP
State Machine
Rx Shift Register
Tx Shift Register
Rx Shadow Register
Tx Shadow Register
8
8
Control
Rx Data
Tx Data
To CPU Interface & Rx/Tx Buffer’s
HCS12 Technical Training, Rev 2.0
Module 11- BDLC, Slide 17
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
BDLC J1850 BUS ERROR
SUMMARY
Error Condition
BDLC Function
Bus short to Vbatt.
The BDLC will not transmit until the bus is idle
Bus short to Gnd.
Thermal overload will shutdown physical interface.
Fault condition is reflected in BSVR as invalid symbol.
Invalid Symbol:
BDLC receives invalid bits(noise)
The BDLC will abort transmission immediately.
Invalid symbol interrupt will be generated
Framing Error
Invalid Symbol interrupt will be generated. The BDLC will wait for SOF.
CRC Error
CRC error interrupt will be generated. The BDLC will wait for SOF.
BDLC Receives Break symbol
The BDLC will wait for the next valid SOF.
Invalid symbol interrupt will be generated
Invalid Symbol:
BDLC send an EOD but receives
an active symbol.
Invalid symbol interrupt will be generated.
The BDLC will wait for SOF.
HCS12 Technical Training, Rev 2.0
Module 11- BDLC, Slide 18
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.