Transcript Resets & Interrupts

Resets
&
Interrupts
HCS12 Technical Training
Module 5 – Resets & Interrupts, Slide 1
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
• Power-On Reset
• External Hardware Reset
• Crystal Monitor
• Computer Operating Properly
• Real time interrupt
HCS12 Technical Training
Module 5 – Resets & Interrupts, Slide 2
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
Power On Reset
• Initiated by positive transition on VDD.
• 8192 E clock delay is built in to allow oscillator to stabilize.
8192 ECLK
Cycles
128 ECLK
Cycles
64 ECLK
Cycles
VDD
CPU CLK
DATA BUS/
ADDRESS BUS
V
F
FFFE
FFFE
P
1st Opcode
V - VECTOR FETCH
F - FREE CYCLE
P - PROGRAM FETCH
IRESET
Internal Reset is held low by MCU For about 8192 E clocks
• In General: Subsystems and control bits are initialized to have least effect on system
( I.e. interrupts masked, ports read only, serial communication disabled,...)
HCS12 Technical Training
Module 5 – Resets & Interrupts, Slide 3
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
P
2nd Opcode
P
3rd Opcode
External & Internal
Resets
96 E Clocks
64 ECLK
CYCLES
32 ECLK
CYCLES
CPU CLK
DATA BUS/
ADDRESS BUS
FFFE
FFFE
1st Opcode 2nd Opcode
RESET
IRESET
SAMPLE
PIN
• RESET pin asserted for > 2 E clocks.
• RESET pin must negate before reset service can begin.
• No delay to stabilize oscillator.
HCS12 Technical Training
Module 5 – Resets & Interrupts, Slide 4
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
3nd Opcode
Crystal Monitor (1 of 2)
Useful for:
1. Automatic Reset from a slow or stopped clock.
2. Improves fault tolerance of system.
Description:
If the E clock drops below a frequency of 10 KHZ* and
the Crystal Monitor function has been enabled, then:
1. system reset is asserted on the external reset pin.
2. Crystal Monitor vector is fetched.
Else
Enter Self Clock Mode if Enabled
* IF E CLOCK FREQUENCY > 10KHz and < 500KHz, THEN A CLOCK
MONITOR RESET MAY OCCUR. ( NOT GUARANTEED )
Note: Crystal Monitor Time-out range 2usec - 150 usec.
HCS12 Technical Training
Module 5 – Resets & Interrupts, Slide 5
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
Crystal Monitor (2 of 2)
PLLCTL - CRG PLL Control Register
Address Offset
$0006
CME - Crystal Monitor Enable
1 = Monitor is enabled
0 = Monitor is disabled
Crystal Monitor function can be enabled/ disabled at any time.
When the Crystal Monitor is enabled, a slow or stopped clocks, (including the Stop
instruction) causes a crystal failure to:
1. Reset the MCU (Fetch CM Vector from $FFFC-$FFFD)
or
2. Enter self-clock mode
PINS:
1. RESET
– Asserted for 64 E clocks.
HCS12 Technical Training
Module 5 – Resets & Interrupts, Slide 6
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
Crystal Loss/Stop & Reset Recovery Sequence
Stop Instruction
Clock Failed
CME = 1
&
SCME =0
?
Power-On
Yes
CME = 1
&
SCME =0
?
Yes
MCU Resets
MCU Resets
No
No
Stop Mode
No
Interrupt
?
Clock
?
Yes
SCME =1
?
Count 8192
OSCLK
Note2:Self Clock Mode Frequency
Range = 2.5MHZ - 5.5MHZ
Yes
Yes
Clock
?
No
Clock
?
No
No
Assert
SCM & SCMIF
Yes
No
MCU
Enters Self CM
Wait
for Clock
Yes
Note1:Crystal Monitor Timeout Range 6 - 18.5 us
Count 8192 OSCLK
Count 8192 OSCLK
Clocks Released
Negate SCM
Clocks resume
Normal Operation
Yes
Resume
Normal Operation
HCS12 Technical Training
Module 5 – Resets & Interrupts, Slide 7
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
Clock
?
No
Computer Operating Properly (1 of 3)
Useful for:
1. Insuring that the MCU does not get "hung up"
for an extended period of time.
2. Improves fault tolerance of system.
Description:
If the COP rate select bits are not “0” and if the watchdog timer
is not reset within a specified time period:
1. Then a system reset is asserted on the external reset pin.
2. COP vector is fetched ( $FFFA-$FFFB )
Pins:
1. Reset
- Asserted for 64E clocks.
HCS12 Technical Training
Module 5 – Resets & Interrupts, Slide 8
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
Computer Operating Properly (2 of 3)
COPCTL - CRG COP Control Register
Address Offset
$0008
WCOP - Window COP Mode
1 = Window COP operation (Writes to ARMCOP Register must occur in the last 25% of selected period).
0 = Normal COP operation
CR[2:0] - COP Watchdog Timer Rate Select
COPCTL : Write Once in user mode, anytime in test mode.
A write to COPCTL will initialize COP counter .
ARMCOP - CRG COP Arm/Reset Timer
Address Offset
$000E
– Software writes $55 followed by $AA to ARMCOP, to reset internal COP counter.
PINS
1. RESET
Asserted for 64 E clocks
HCS12 Technical Training
Module 5 – Resets & Interrupts, Slide 9
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
COP Time-out Period Select (3 OF 3)
CR[2:0] = 000 - COP is Off
OSCCLK
COP Rate Selection Bit Definition
COP Divider Chain
Time-Out = WindowEnd = OscClkPeriod * (OscClkDivider +3)
Window-Start = OscClkPeriod * ((0.75* OscClkDivider) + 9)
HCS12 Technical Training
Module 5 – Resets & Interrupts, Slide 10
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
Determining Reset Source
START
N
CLOCK
FAILS
CME=1
?
Y
ASSERT
RESET PIN
FOR 64
E-CLOCK
CYCLES
CLOCK
MONITOR
STATUS IS
LATCHED
END
GO TO
RESET
SERVICE
ROUTINE
EXTERNALLY
ASSERTED
RESET
Y
Y
RESET PIN
NEGATION,
32 E-CLOCK
CYCLES
ALLOWED
GO TO
COP
ROUTINE
GO TO
CRYSTAL
MONITOR
ROUTINE
RESET
PIN STILL
LOW
?
N
RESET
PIN STILL
LOW?
CRYSTAL
MONITOR
SYSTEM
RESET
?
HCS12 Technical Training
Module 5 – Resets & Interrupts, Slide 11
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
N
INTERRUPT EXCEPTIONS
INTERRUPT STACK
PRIORITIES
VECTORS
INTERRUPT FLOW
INTERRUPT INSTRUCTIONS
STANDBY MODES
HCS12 Technical Training
Module 5 – Resets & Interrupts, Slide 12
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
Interrupt Sources
From
COP
EXTERNAL BUS
COP
RESET
From
P.I.T
P.I.T IRQ
From
Crystal Monitor
C.M
RESET
INTERNAL BUS
ECT IRQ’S
SPI IRQ’S
IRQ
XIRQ
RESET
SCI IRQ’S
INTERRUPT
&
RESET
VECTOR
GENERATION
&
PRIORITY
Other IRQ’S
Resets
SWI
ILLOP
The MC9S12DP256
can generate over 50
Interrupt requests
I_Vector
X_Vector
IPEND
XPEND
HCS12 Technical Training
Module 5 – Resets & Interrupts, Slide 13
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
Interrupt Stacking Order
SP after operation
SP before operation
SP-9
CCR
SP-8
D
SP-6
X
SP-4
Y
SP-2
PC
xx
SP
When HCS12 acknowledges an interrupt, it stacks registers,
then determines which vector to take. ( different from hc11 ).
Note: Stack operation is performed in 5-bus cycles even if SP is misaligned.
HCS12 Technical Training
Module 5 – Resets & Interrupts, Slide 14
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
Non-Maskable Exception
Priority
• More than 40 interrupt sources.
• Separate vector for each Reset / Interrupt source.
• 6 Non-Maskable sources
1. RESET
2. Crystal Monitor*
3. COP WATCHDOG*
4. TRAP
5. XIRQ**
6. SWI
* Can generate external Reset
** Once enabled, cannot be masked
HCS12 Technical Training
Module 5 – Resets & Interrupts, Slide 15
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
Interrupt Vector Table (1 of 3)
(64 Exception Vector Entries)
HCS12 Technical Training
Module 5 – Resets & Interrupts, Slide 16
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
Interrupt Vector Table (2 of 3)
HCS12 Technical Training
Module 5 – Resets & Interrupts, Slide 17
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
Interrupt Vector Table (3 of 3)
HCS12 Technical Training
Module 5 – Resets & Interrupts, Slide 18
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
Interrupt Request Pins Control
IRQ - Masked by I-Bit in CCR
HCS12
XIRQ - Masked by X-Bit in CCR*
* Once enabled, can not be masked
INTCR - Interrupt Control Register
Address Offset
$001E
Write once
IRQE - Interrupt Select Edge Sensitive
1 = IRQ PIN is configured for negative edge
0 = IRQ PIN is configured for level sensitive
IRQEN - External IRQ Enable
1 = IRQ PIN is connected to interrupt logic
0 = IRQ PIN is disconnected from interrupt logic
Note: XIRQ and IRQ have internal pull-ups and enabled out of reset
Pull-up can be turned off by clearing PUPEE in PUCR register
HCS12 Technical Training
Module 5 – Resets & Interrupts, Slide 19
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
Interrupt & Priority Control
An interrupt source can be elevated to highest priority( i.e. 7 )
by writing to HPRIO register ( bits 7 - 1 ).
Interrupt priority can only be changed when I = 1 in CCR
HPRIO - High Priority Register
Address Offset
$001F
To promote an interrupt the user writes the least significant byte of the
associated interrupt vector address to this register. If an unimplemented
vector address or a non I-masked vector address (value higher than $F2)
is written, then $FFF2 vector will be the default. (highest priority interrupt).
HCS12 Technical Training
Module 5 – Resets & Interrupts, Slide 20
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
Interrupt Flow
SOFTWARE
INTERRUPT
STACK MPU
REGISTER
CONTENTS
HARDWARE
INTERRUPT
N
MASK
SET?
Y
CONTINUE MAIN
PROGRAM
SET I BIT
IN CCR
$FF80
LOAD INTERRUPT
VECTOR INTO
PROGRAM COUNTER
VECTOR
TABLE
$FFFF
EXECUTE INTERRUPT
SERVICE ROUTINE
HCS12 Technical Training
Module 5 – Resets & Interrupts, Slide 21
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
Interrupt Instructions
FUNCTION
MNEMONIC
OPERATION
SOFTWARE INTERRUPT
SWI
REGS  M SP
SP-9  SP
1 I
M FFF6  PC
M FFF7  PC
RETURN FROM INTERRUPT
RTI
H
L
M SP  REGS
SP + 9  SP
Note: RTI instruction will not unstack if another interrupt is pending.
HCS12 Technical Training
Module 5 – Resets & Interrupts, Slide 22
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
Real-Time Interrupt
Useful for:
1. Keep track of time
2. Initiate tasks on periodic bases.
Description:
When a time-out occurs:
1. Interrupt request to CPU is generated, if enabled
2. RTI vector is fetched ( $FFF0-$FFF1 )
HCS12 Technical Training
Module 5 – Resets & Interrupts, Slide 23
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
Real-Time Interrupt Flow Chart
START
INCREMENT
INTERNAL
COUNTER
COUNT
IS AT AN
INTERVAL
?
Y
RTIF GOES
to 1
N
N
END
RTIE=1
?
Y
ASSERT
INTERRUPT
HCS12 Technical Training
Module 5 – Resets & Interrupts, Slide 24
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
Real-Time Control/Status Registers
RTICTL - Real-Time Clock Control Register
Reset:
Bit 7
6
0
0
5
0
RTR[6:4] - Real-Time Interrupt Prescale Rate Select
4
Address Offset
$0007
3
0
2
0
1
0
0
0
OSCCLK
RTI Divider Chain
RTR[3:0] - Real-Time Interrupt Modulus Counter Select
Note: To initialize the internal RTI
counter, write to the RTICTL register.
HCS12 Technical Training
Module 5 – Resets & Interrupts, Slide 25
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
0
PLL Control Registers
CRGFLG - CRG Flag Register
Address Offset
$0003
RTIF — Real Time Interrupt Flag
RTIF bit is automatically set to one at the end of every RTI period.
This flag can only be cleared by writing a 1.
0 = Time-out has not yet occurred.
1 = Set when the time-out period is met.
CRGINT - CRG Interrupt Enable Register
RTIE - Real-Time Interrupt Enable
0 = Interrupt is disabled
1 = Interrupt is disabled
HCS12 Technical Training
Module 5 – Resets & Interrupts, Slide 26
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
Address Offset
$0004
S12 Oscillator Layout
RESET signal noise free. Don’t
use for external signals and / or
add series filtering.
PLL Filter cct
Optional dc blocking
capacitor goes in the
EXTAL line here
Oscillator components
on MCU side of board
- no vias
No ground or power planes
under Oscillator components,
to minimise parasitics.*
C2
C1
R2
Y1
C3
TEST
XTAL
EXTAL
VSSPLL
C4
XFC
VDDPLL
RESET
To 5V ‘star’
point at VSSA
C7
C8
C9
C5
C6
VDDR
VSSR
PE4
Connection
to ground net/plane
No other signals should be routed
near, or under the crystal components
or the PLL components because
these circuit nodes are very
susceptible to coupled electric noise.
Good isolation of PLL /
Oscillator Power supply.
C5 = 1nf, C6 = 100nF.
Low impedance, no vias.
* NOTE: EMC
considerations should
also be taken into
consideration
HCS12 Technical Training
Module 5 – Resets & Interrupts, Slide 27
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.