Transcript Chapter 2 - Part 1 - PPT - Mano & Kime

Registers
Computer Architecture
CS 215
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Registers & Counters
 Register


Collection of storage elements
Set of flip-flops
 Counter

Register that cycles through a sequence of
states (values)
2
2-bit Register
 Independent
In1
data lines
 Shared


D Q
Q1
Q
Clock pulse
Write
enable
CP
W
In0
D Q
Q0
Q
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3
Register Design Models
 Large numbers of states and input
combinations as n becomes large
 State diagram/state table model is not
feasible
 Options?


Add predefined combinational circuits to registers
Design individual cells using the state
diagram/state table model and combine them into
a register
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Register Storage
 Expectations:


Store information for multiple clock cycles
“store” or “load” control signal
 Reality:

D flip-flop loads information on every clock
cycle
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Register Storage
 Options:
1.
2.
3.
Signal to block the clock to the register
Signal to control feedback of the output of
the register back to its inputs
Use other SR or JK flip-flops which for
(0,0) applied store their state
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Clock Gating
Clock
Load
Gated Clock to FF
Gated Clock = Clock + Load
Advantages?
Disadvantages?
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Load-Controlled Feedback
 2 to 1
Mux used
to control
load
operation
 Note
feedback
loops
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2-to-1 Multiplexers
A1
D Q
Load
In1
Y1
C
A0
D Q
C
Y0
In0
Clock
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Register Transfer Operations
 Movement and processing of data
stored in registers
 Components



set of registers
operations
control of operations
 Microoperations


Elementary operations
Load, count, shift, add, bitwise "OR", etc.
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Register Notation
R
15
8 7
0
PC(H)
PC(L)





76543210
15
0
R2
Letters and numbers denotes a register
Parentheses ( ) denotes a range of register bits
Arrow () denotes data transfer
Comma separates parallel operations
Brackets [ ] specifies a memory address
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Conditional Transfer
 K1: (R2  R1)

If (K1 =1) then (R2  R1)
K1
R1
n
Load
R2
Clock
Clock
K1
Transfer Occurs Here
No Transfers Occur Here
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Microoperations
 Logical Groupings:




Transfer - move data from one set of registers to another
Arithmetic - perform arithmetic on data in registers
Logic - manipulate data or use bitwise logical operations
Shift - shift data in registers
Arithmetic operations
+ Addition
– Subtraction
* Multiplication
/ Division
Logical operations
 Logical OR
 Logical AND
 Logical Exclusive OR
 Not
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Control Expressions
 Appear to the
left of
operations
separated by a
colon
 Specify the
logical
condition for
the operation
to occur
 Example:
X’ K1 : R1  R1 + R2
X K1 : R1  R1 + R2’ + 1
 Variable K1 enables the add or
subtract operation.
 If X =0, then X’ =1 so K1 = 1,
activating the addition of R1
and R2.
 If X = 1, then X K1 = 1,
activating the addition of R1
and the two's complement of
R2 (subtract).
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Arithmetic Microoperations
Symbolic Designation
R0  R1 + R2
R0  R1
R0  R1 + 1
R0  R2 + R1 + 1
R1  R1 + 1
R1  R1 – 1
Description
Addition
Ones Complement
Two's Complement
R2 minus R1 (2's Comp)
Increment (count up)
Decrement (count down)
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Logical Microoperations
Symbolic
Designation
R0  R1
R0  R1  R2
R0  R1  R2
R0  R1  R2
Description
Bitwise NOT
Bitwise OR (sets bits)
Bitwise AND (clears bits)
Bitwise EXOR (complements bits)
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Shift Microoperations
Symbolic
Designation
R1  sl R2
R1  sr R2
Description
R1
10010010
01100100
Operation
R1  sl R2
R1  sr R2
Shift Left
Shift Right
 Note: These shifts "zero fill". Sometimes a separate flipflop is used to provide the data shifted in, or to “catch” the
data shifted out.
 Other shifts are possible (rotates, arithmetic)
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Register Transfer Structures
 Multiplexer-Based Transfers - Multiple inputs are
selected by a multiplexer dedicated to the register
 Bus-Based Transfers - Multiple inputs are selected by
a shared multiplexer driving a bus that feeds inputs
to multiple registers
 Three-State Bus - Multiple inputs are selected by
3-state drivers with outputs connected to a bus that
feeds multiple registers
 Other Transfer Structures - Use multiple
multiplexers, multiple buses, and combinations of all
the above
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Multiplexer-Based Transfers
 Multiplexers connected to register inputs produce
flexible transfer structures (Note: Clocks are omitted
for clarity)
Load
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R2
K2
K1
n
Load
n
Load
S
0
MUX
1
n
R0
R1
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Shift Registers
B
A
In
DQ
DQ
C
DQ
Out
DQ
CP
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 Move data laterally within the register
 Simplest case, the shift register is a set of
D flip-flops connected in a row
 Data input, In, is called a serial input or the shift
right input
 Data output, Out, is often called the serial output
 The vector (A, B, C, Out) is called the parallel output.
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Parallel Load Shift Registers
 By adding a MUX between each shift
register stage, data can be shifted or
loaded
 If SHIFT is low, A and B are replaced
by the data on DA and DB lines, else
data shifts right on each clock
DA
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DB
A
IN
D
Q
B
D
Q
SHIFT
CP
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