Transcript Chapter 6 - Part 2 - PPT - Mano & Kime
SYEN 3330 Digital Systems
Chapter 7 – Part 3
SYEN 3330 Digital Systems Jung H. Kim 1
Datapath and Operations
Review of Digital Logic Systems
Digital System – a sequential circuit made up of interconnected flip flops and gates.
Gates – implement the logic functions.
Functional Blocks – a collection of gates implementing a specific function. (e.g. multiplexers, adders, shifters, etc.) Flip-flops – provide the state variables.
Registers – a collection of flip-flops.
Memory – a large collection of flip-flops (or other storage elements) combined with a method of accessing the flip-flops.
We will study how to organize these elements into two interacting subsystems – Control and Datapath
SYEN 3330 Digital Systems Chapter 7-3 Page 2
Review: A Computer
Datapath: performs basic operation on data stored in registers.
CPU (Central Processing Unit): Determines a sequence of data processing operations to be performed in the datapath portion.
Control: configures data transfers and establish operations to be performed.
Memory: -- A regular array of data storage elements.
Input/Output: -- A collection of devices that store, display and convert information.
Memory CPU Control Datapath Input/Output SYEN 3330 Digital Systems Chapter 7-3 Page 3
Datapath and Control Unit
Control Unit: Determines a sequence of data processing operations to be performed in the
Control Inputs Control Unit Control Status Datapath Data Output
datapath portion.
Datapath: Performs
Control Outputs Data Inputs
basic operation on data stored in registers.
Control: signals that configure data transfers and establish operations to be performed.
Status: -- signals that represent the state of data, such as overflow bits, “zero” tests, etc. These signals are tested to change the sequence of operations.
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Register Transfer Operations
Resisters – a collection of binary storage flip-flops organized in some logical fashion.
Register Transfer Operations – the movement of data stored in registers and the processing performed on the data.
Three basic components:
Set of registers Operations
Control
Elementary Operations
Load, count, shift, add, bitwise “OR”, etc.
Elementary operations are called micro-operations.
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Register Transfer
Register Nomenclature R 7 6 5 4 3 2 1 0 15 8 PC(H) 7 0 PC(L) 15 0 R2
Letters and numbers – denotes a register (ex. R2, PC, IR) Parentheses ( ) – denotes a range of register bits (ex. R1(1), PC(7:0), AR(L)) Arrow (
) – denotes data transfer (ex. R1
R2, PC(L)
R0) Comma – separates parallel operations Brackets [ ] – Specifies a memory address (ex. R0
R3
M[PC]) M[AR],
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Conditional Transfer
If (K1 = 1) then (R2
R1) is
shortened to K1: (R2
R1) where K1 is a control variable specifying a conditional execution condition.
Conditional execution is used to modify the sequence of microoperations.
K1 Clock Clock K1 R1 n Load R2 Transfer Occurs Here
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Microoperations
Logical Groupings:
Transfer – move data from one set of registers to another.
Arithmetic – perform arithmetic on data in registers.
Logic – manipulate data or use bitwise logical operations.
Shift – shift data in registers.
Arithmetic operations (word – wide) + Addition – Subtraction * Multiplication / Division
Logical operations (bitwise)
Logical OR
Logical AND
Logical Exclusive OR
¯
Not
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Example
Microoperations
Add the content of R1 to the content of R2 and place the result in R1. R1
R1 + R2
Multiply the content of R1 by the content of R6 and place the result in PC. PC
R1 * R6
Exclusive OR the content of R1 with the content of R2 and place the result in R1. R1
R1
R2
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Example Microoperations (Continued)
Take the 1’s Complement of the contents of R2 and place it in the PC. PC
R2
On condition K 1 OR K 2 , Logical bitwise OR the content of R1 with the content of R3 and place the result in R1. (K 1 +K 2 ): R1
R1
R3
Note: “+” (as in K 1 + K 2 ) and
both mean “OR”!
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Control Variables
The control variable for an operation appears to the left of the operation and is separated by a colon.
Control variables specify the logical conditions for the operation.
Control Variable values of:
Logic “1” – the operation takes place.
Logic “0” – the operation is inhibited.
Examples: X’
X
K 1 K 1 : R1
: R1
R1 + R2 R1 + R2’ + 1 Variable K 1 enables the add or subtract operation.
If X=0, then X’ = 1 so X’
K 1 = 1, activating add of R1 and R2.
If X=1, then X
K 1 = 1, activating add of R1 and the two’s comp. of R2 (Subtract)
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Arithmetic
Microoperations
From Table 7-3 Symbolic Designation R0
R1 + R2 R0
R1 R0
R1 + 1 R0
R2 + R1 + 1 R1
R1 + 1 R1
R1 – 1 Description Addition One’s Complement Two’s Complement R2 minus R1 (2’s Comp) Increment (count up) Decrement (count down)
Note that any register may be specified for source1, source2, or destination.
These simple microoperations operate on the whole word – except for 1’s complement which is a bitwise operation.
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Logical
Microoperations
From Table 7-4 Symbolic Designation R0
R1 R0
R1
R2 R0
R1
R2 R0
R1
R2 Description Bitwise NOT Bitwise OR (sets bits) Bitwise AND (clears bits) Bitwise EXOR (complements bits)
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Logical Microoperations (Continued)
Let R1 = 10101010, and R2 = 11110000 Then after “Operation”, R0 Becomes: R0 01010101 11111010 10100000 01011010 Operation R0
R1 R0
R1
R2 R0
R1
R2 R0
R1
R2
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Shift
Microoperations
From Table 7-5: Symbolic Designation R1
sl R2 R1
sr R2 Description Shift Left Shift Right
Let R2 = 11001001 Then after “Operation”, R1 becomes: R1 10010010 01100100 Operation R1
sl R2 R1
sr R2
Note: These shifts “zero fill”. Sometimes a separate “link” bit can be used to provide the data shifted in, or to “catch” the data shifted out.
Other shifts are possible (circular, arithmetic).
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Register Transfer Structures
Multiplexer-Based Transfers
Register inputs are connected to multiple sources via a multiplexer.
Bus-Based Transfers
Register inputs are connected to a single bus driven by a multiplexer.
Three-State Bus
Register inputs and outputs are connected to a single bus via tri-state drivers.
Memory Transfer
Registers provide a source for Memory Addresses and a source or sink for Memory Data.
Other Transfer Structure
Use multiple multiplexers, multiple busses, combinations of all the above, etc.
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Multiplexer-Based Transfers
Multiplexers connected to register inputs produce flexible transfer structures: (Note: Clocks are left off for clarity) The transfer are: K1: R0
K2
R1 K1’: R0
R2
Load R2
K1 K2
Load R1
n n 0
S
1 MUX n
Load R0 SYEN 3330 Digital Systems Chapter 7-3 Page 17
MUX-Based Transfers (Continued)
Multiplexers connected to each register input produces a very flexible transfer structure: n n
L0
0 S MUX 1 n
Load R0
What transfers are possible with this structures? How many operations can occur in parallel?
SYEN 3330 Digital Systems
n n
L1
0 S MUX 1 n
Load R1
n n
L2
0 S MUX 1 n
Load R2 Chapter 7-3 Page 18
Bus-Based Transfers
A single input bus driven by a multiplexer limits the available transfers:
What transfers can occur here?
L0
n
Load R0
S1 S0 n n n S1 S0 0 1 MUX 2 n
n
L1 Load R1 L2
n
Load R2 SYEN 3330 Digital Systems Chapter 7-3 Page 19
Three-State Bus
The three-input MUX can be replaced by 3 – state buffers. Transfers are still limited
What transfers are allowed here?
SYEN 3330 Digital Systems L0
n n
Load R0
E0
L1
n E1 n
Load R1 L2
n n
Load R2
E2
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Memory Transfer
And require
DATA (write operations),
Memory operations require:
ADDRESS Or provide
DATA (read operations)
Typically:
There can be more than one memory address source in a system
There can be more than one data source or data sink in a system
Some structure of busses and multiplexers is needed to access the memory.
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Other Transfer Structures
Fast systems require that parallel operations occur within the same clock.
Parallel operations imply “resources” required to move the data
SO:
• •
Multiple busses are used, and Multiplexers are used to select input sources.
THIS REQUIRES MOER HARDWARE!
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Other Transfer Structures (Continued)
What transfers does this system allow?
SYEN 3330 Digital Systems
n n S0 S 0 MUX 1 n n S1 S 0 MUX 1 n n S2 S 0 MUX 1 L0 n n n E0a E0b Load R0 L1 n n n E1a E1b n n n E2a E2b Load R1 L2 Load R2
Chapter 7-3 Page 23