Transcript Chap. 4 Register Transfer and Microoperations

Chap. 4 Register Transfer and Microoperations

4-1
4-1 Register Transfer Language
 Microoperation
 The operations executed on data stored in registers(shift, clear, load, count)
 Internal H/W Organization(best defined by specifying)
1. The set of registers(register의 개수, 종류, 기능)
2. The sequence of microoperations
3. The sequence control of microoperations
 Register Transfer Language
 The symbolic notation used to describe the microoperation transfer among
registers
» The use of symbols instead of a narrative explanation provides an organized and
concise manner


A convenient tool for describing the internal organization of digital computers in
concise and precise manner
4-2 Register Transfer
 Registers : Fig. 4-1
 Designated by Capital Letter(sometimes followed by numerals) : MAR(Memory
Address Register), PC(Program Counter), IR(Instruction Register), R1(Processor
Register)
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Chap. 4 Register Transfer and Microoperations
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


The individual F/Fs in an n-bit register : numbered in sequence from 0(rightmost
position) through n-1
The numbering of bits in a 16-bit register : marked on top of the box
A 16-bit register partitioned into two parts : bit 0-7(symbol “L” Low byte), bit 815(symbol “H” High byte)
 Register Transfer : Information transfer from one register to another
 R2  R1 (transfer of the content of register R1 into register R2)
» The content of the source register R1 does not change after the transfer
 Control Function : The transfer occurs only under a predetermined control condition
 The transfer operation is executed by the hardware only if P=1 : Fig. 4-2
if ( P  1) then ( R 2  R1)
P : R 2  R1

=
A comma is used to separate two or more operations(Executed at the same time)
T : R 2  R1, R1  R 2
 Basic Symbols for Register Transfer : Tab. 4-1
Symbol
Description
Letters(and numerals) Denotes a register
Parentheses ( )
Denotes a part of a register
Arrow <-Denotes transfer of information
Comma ,
Separates two microoperations
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Examples
MAR, R2
R2(0-7), R2(L)
R2 <-- R1
R2 <-- R1, R1 <-- R2
Chap. 4 Register Transfer and Microoperations
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4-3

4-3 Bus and Memory Transfers
 Common Bus
 A more efficient scheme for transferring information between registers in a
multiple-register configuration
 A bus structure = a set of common lines
 Control signals determine which register is selected
» One way of constructing a common bus system is with multiplexers
» The multiplexers select the source register whose binary information is place on the bus

The construction of a bus system for four registers : Fig. 4-3
» 4 bit register X 4
» Four 4 X 1 Multiplexers
» Bus Selection : S0, S1
S1
0
0
1
1

S0
0
1
0
1
Register selected
A
B
C
D
4-line
common
bus
S1
S0
4*1
MUX 3
3
2
3
2 1
4*1
MUX 2
1 0
4*1
MUX 1
3 2
1
0
3
2
3
1
0
3 2
4*1
MUX 0
1 0
3
2
1
0
1
3
2
1 0
8 Registers with 16 bit
» 16 X 1 mux 8 개 필요
0
Register D
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2
Register C
Chap. 4 Register Transfer and Microoperations
0
Register B
Register A
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 Bus Transfer
 The content of register C is placed on the bus, and the content of the bus is
loaded into register R1 by activating its load control input
Bus
Bus  C, R1  Bus
R1  C
 Three-State Bus Buffers



=
R1 Register
C Register
n
A bus system can be constructed with three-state gates instead of multiplexers
Tri-State : 0, 1, High-impedance(Open circuit)
Buffer
» A device designed to be inserted between other devices to match impedance, to
prevent mixed interactions, and to supply additional drive or relay capability
» Buffer types are classified as inverting or noninverting

Tri-state buffer gate : Fig. 4-4
» When control input =1 : The output is enabled(output Y = input A)
» When control input =0 : The output is disabled(output Y = high-impedance)
Normal
input A
If C=1, Output Y = A
If C=0, Output = High-impedance
Control
input C
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Chap. 4 Register Transfer and Microoperations
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4-5
 The construction of a bus system with tri-state buffer : Fig. 4-5
 The outputs of four buffer are connected together to form a single bus line(Tristate buffer이기 때문에 가능)
 No more than one buffer may be in the active state at any given time(2 X 4
Decoder사용으로 해결)
 To construct a common bus for 4 register with 4 bit : Fig. 4.5와 같은 회로 4 개
필요(register 개수가 늘어나면 decoder의 입력 증가 및 buffer 개수 증가)
A0
Bus line for bit 0
B0
C0
AR: Address Reg.
DR: Data Reg.
M : Memory Word(Data)
D0
Select input
Enable input
S1
0
S0
1
2*4
decoder
2
E
3
READ :
DR  M [ AR]
WRITE :
M [ AR]  R1
 Memory Transfer
 Memory read : A transfer information into DR from the memory word M selected
by the address in AR
 Memory Write : A transfer information from R1 into the memory word M selected
by the address in AR
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Chap. 4 Register Transfer and Microoperations
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
The 4 types of microoperation in digital computers
 Register transfer microoperation : Sec 2-4 와 Sec 4-2에서 이미 학습
 Arithmetic microoperation
Sec 4-4, 4-5,
4-6에서 학습
 Logic microoperation
 Shift microoperation

Sec 4-7에서 3
개를 모두 통합
4-4 Arithmetic Microoperation
 Arithmetic Microoperation : Tab. 4-3
 Negate : 2’s complement R2  R2  1
 Subtraction : R1 + 2’s complement of R2 R 3  R1  R 2  R1  ( R 2  1)
 Multiplication(shift left), Division(shift right)
 4-bit Binary Adder : Fig. 4-6
 Full adder = 2-bits sum + previous carry
 c0(input carry), c4(output carry)
B3
A3
B2
A2
B1
A1
B0
A0
FA
FA
FA
FA
S3
S2
S1
S0
C0
C4
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 4-bit Binary Adder-Subtractor : Fig. 4-7
 M =0 : Adder
B  M + C = B  0 + 0 = B,  A + B
 M =1 : Subtractor B  M + C = B  1 + 1 = B’ + 1= -B(2’s comp), A - B
B3 A3
B2 A2
B1 A1
B0 A0
M
FA
FA
FA
FA
C0
C4
S3
S2
S1
S0
 4-bit Binary Incrementer
 Sequential circuit implementation by using binary counter : Fig. 2-10
 Combinational circuit implementation by using Half Adder : Fig. 4-8
B3
x
B2
y
x
B1
y
x
B0
y
x
1
y
Always added to 1
HA
C
C4
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S
S3
HA
C
S
S2
HA
C
S
S1
HA
C
S
S0
Chap. 4 Register Transfer and Microoperations
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 Arithmetic Circuit
 One composite arithmetic circuit in Tab. 4-3 :
Fig. 4-9
 D= A0(X0) + B0(Y0) + Cin
» B0 : S0, S1에 따라 B, B, 0, 1
» Tab. 4-4의 Input Y = B
Select Input Output
Microoperation
S1 S0 Cin Y D=A+Y+Cin
0 0 0 B D=A+B
Add
0 0 1 B D=A+B+1 Add with carry
0 1 0 B' D=A+B'
Subtract with borrow
0 1 1 B' D=A+B'+1 Subtract
1 0 0 0 D=A
Transfer A
1 0 1 0 D=A+1
Increment A
1 1 0 1 D=A-1
Decrement A
1 1 1 1 D=A
Transfer A
Cin
S0
S1
C0
X0
A0
S0
0
B0
1
D0
FA
S1
4*1
MUX
Y0
C1
2
3
C1
X1
A1
S0
0
B1
1
D1
FA
S1
4*1
MUX
Y1
C2
2
3
C2
X2
A2
S0
0
B2
1
D2
FA
S1
4*1
MUX
Y2
C3
2
3
C3
X3
A3
A+1111=A-1
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A+B’=A+B’+1-1
= A-B-1
A-1+1=A
S0
0
B3
1
D3
FA
S1
4*1
MUX
Y3
C4
2
0
Chap. 4 Register Transfer and Microoperations
3
Cout
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
4-5 Logic Microoperation
 Logic microoperation
 Logic microoperations consider each bit of the register separately and treat
them as binary variables
» exam) P : R1  R1  R2

Arithmetic에서
1’s Complement
와 동일
1010 Content of R1
+ 1100 Content of R2
0110 Content of R1 after P=1
Special Symbols
» Special symbols will be adopted for the logic microoperations OR(/), AND(), and
complement(a bar on top), to distinguish them from the corresponding symbols used
to express Boolean functions
» exam) P  Q : R1  R 2  R3, R 4  R5  R6
Logic OR
S0
S1
Arithmetic ADD
 List of Logic Microoperation
 Truth Table for 16 functions for 2 variables : Tab. 4-5
 16 Logic Microoperation : Tab. 4-6
All other Operation
Computer System Architecture
Chap. 4 Register Transfer and Microoperations
S0
4*1
MUX
Ai
0
Bi
 Hardware Implementation
 16 microoperation
Use only 4(AND, OR, XOR, Complement)
 One stage of logic circuit : Fig. 4-10
can be derived
S1
E
1
2
3
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i
4-10
 Some Applications
 Logic microoperations are very useful for manipulating individual bits or a
portion of a word stored in a register
 Used to change bit values, delete a group of bits, or insert new bit values
 Selective-set A  A  B
» The selective-set operation sets to 1 the bits in register A where there are corresponding
1’s in register B. It does not effect bit positions that have 0’s in B

1
0

0
0

Selective-complement A  A  B
» The selective-complement operation complements bits in A where there are
corresponding 1’s in B. It does not effect bit positions that have 0’s in B
Selective-clear A  A  B
» The selective-clear operation clears to 0 the bits in A only where there are
corresponding 1’s in B
Selective-mask A  A  B
» The mask operation is similar to the selective-clear operation except that the bits of A
are cleared only where there are corresponding 0’s in B
1010 A before
1100 B(Logic Operand)
1110 A After
Selective-set
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1010 A before
1100 B(Logic Operand)
0110 A After
Selective-complement
1010 A before
1100 B(Logic Operand)
0010 A After
Selective-clear
Chap. 4 Register Transfer and Microoperations
1010 A before
1100 B(Logic Operand)
0010 A After
Selective-mask
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
Insert
» The insert operation inserts a new value into a group of bits
» This is done by first masking the bits and then ORing them with the required value
1) Mask
0110 1010 A before
0000 1111 B mask
0000 1010 A after mask

2) OR
0000 1010 A before
1001 0000 B insert
1001 1010 A after insert
Clear
0110
0110
0000
A
B
A after clear
Clear A  A  B
» The clear operation compares the words in A and B and produces an all 0’s result if the
two numbers are equal

4-6 Shift Microoperations
 Shift Microoperations : Tab. 4-7
 Shift microoperations are used for serial transfer of data
 Three types of shift microoperation : Logical, Circular, and Arithmetic
 Logical Shift
 A logical shift transfers 0 through the serial input
= The bit transferred to the end position through the serial input is assumed to be 0
during a logical shift(Zero inserted)
R1  shl R1
R 2  shr R 2
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 Circular Shift(Rotate)
 The circular shift circulates the bits of the register around the two ends without
loss of information
R1  cil R1
R 2  cir R 2
 Arithmetic Shift
 An arithmetic shift shifts a signed binary number to the left or right
 An arithmetic shift-left multiplies a signed binary number by 2
 An arithmetic shift-right divides the number by 2
 Arithmetic shifts must leave the sign bit unchanged because the sign of the
number remains the same
 Shift right : R 2  ashr R 2
 Shift left : R 2  ashl R 2
LSB lost
LSB
MSB
Carry out
Sign bit
0 insert
Rn-1 Rn-2
MSB

....
. R1
R0
LSB
Sign reversal occur : Overflow F/F Vs=1
V
s
 Rn 1  Rn 2
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Chap. 4 Register Transfer and Microoperations
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 Hardware Implementation(Shifter) : Fig. 4-12

Serial
input(IR)
4-7 Arithmetic Logic Shift Unit
S
 One stage of arithmetic logic shift unit : Fig. 4-13
S3
S2
S1
S0
Select(S)
MUX
H0
MUX
H1
MUX
H2
MUX
H3
0
1
S
A0
A1
A2
A3
Ci
0
1
One state of
arithmetic
circuit
(Fig. 4.9)
S
0
Select
1
Ci+1
0
1
4*1
MUX
Fi
2
3
Bi
Ai
0
1
Ai-1
Ai+1
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S
One state of
logic circuit
(Fig. 4.10)
Serial
input(IL)
Chap. 4 Register Transfer and Microoperations
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