Transcript Document

Chapter 5
Differential and
Multistage Amplifier
SJTU Zhou Lingling
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Outline
• Introduction
• The CMOS Differential Pair
• Small-Signal Operation of the MOS Differential
Pair
• The BJT Differential Pair
• The differential Amplifier with Active Load
• Frequency Response of the Differential amplifier
• Multistage Amplifiers
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Introduction
• Two reasons of the differential amplifier suited for
IC fabrication:
 IC fabrication is capable of providing matched devices.
 Utilizing more components than single-ended amplifier:
Differential circuits are much less sensitive to noise and
interference.
Differential configuration enable us to bias the amplifier and to
couple amplifier stages without the need for bypass and
coupling capacitors.
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The MOS Differential Pair
• Basic structure of differential pair.
• Characteristics
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The MOS Differential Pair
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Operation with a Common –Mode
Input Voltage
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Operation with a Common –Mode
Input Voltage
• Symmetry circuit.
• Common-mode voltage.
• Current I divides equally between two
transistors.
• The difference between two drains is zero.
• The differential pair rejects the commonmode input signals.
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Operation with a Differential Input
Voltage
The MOS differential
pair with a differential
input signal vid applied.
With vid positive: vGS1 >
vGS2, iD1 > iD2, and vD1 <
vD2; thus (vD2 - vD1) will be
positive.
With vid negative: vGS1 <
vGS2, iD1 < iD2, and vD1 >
vD2; thus (vD2 - vD1) will be
negative.
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Operation with a Differential Input
Voltage
• Differential input voltage.
• Response to the differential input signal.
• The current I can be steered from one transistor to
the other by varying the differential input voltage
in the range:
- 2VOV  vid  2VOV
• When differential input voltage is very small, the
differential output voltage is proportional to it, and
the gain is high.
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Large-Signal Operation
Transfer
characteristic curves
Normalized plots of
the currents in a
MOSFET differential
pair.
Note that VOV is the
overdrive voltage at
which Q1 and Q2
operate when
conducting drain
currents equal to I/2.
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Large-Signal Operation
•
•
•
•
•
Nonlinear curves.
Maximum value of input differential voltage.
When vid = 0, two drain currents are equal to I/2.
Linear segment.
Linearity can be increased by increasing overdrive
voltage(see next slide).
• Price paid is a reduction in gain(current I is kept
constant).
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Large-Signal Operation
The linear range of operation of the MOS differential pair can be extended by
operating the transistor at a higher value of VOV.
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Small-Signal Operation of MOS
Differential Pair
•
•
•
•
•
Linear amplifier
Differential gain
Common-mode gain
Common-mode rejection ratio(CMRR)
Mismatch on CMRR
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Differential Gain
a common-mode
voltage applied to
set the dc bias
voltage at the gates.
vid applied in a
complementary (or
balanced) manner.
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Differential Gain
Signal voltage at the joint source connection must be zero.
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Differential Gain
An alternative way of
looking at the smallsignal operation of
the circuit
.
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Differential Gain
• Differential gain
 Output taken single-ended
vo1
Ad 1 
 - 12 g m RD
vid
 Output taken differentially
vo 2 1
Ad 2 
 2 g m RD
vid
vo
Ad 
 g m RD
vid
 Advantages of output signal taken differentially
• Reject common-mode signal
• Increase in gain by a factor of 2(6dB)
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Differential Gain
MOS differential amplifier with ro and RSS taken into account.
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Differential Gain
Equivalent circuit for determining the differential gain.
Each of the two halves of the differential amplifier circuit is a commonsource amplifier, known as its differential “half-circuit.”
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Differential Gain
• Differential gain
 Output taken single-ended
vo1
Ad 1 
 - 12 g m ( RD // ro )
vid
vo 2 1
Ad 2 
 2 g m ( RD // ro )
vid
 Output taken differentially
vo
Ad 
 g m ( RD // ro )
vid
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Common-Mode Gain
The MOS differential
amplifier with a commonmode input signal vicm.
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Common-Mode Gain
Equivalent circuit for determining the common-mode gain (with ro ignored).
Each half of the circuit is known as the “common-mode half-circuit.”
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Common-Mode Gain
• Common-mode gain
 Output taken single-ended
Acm1  Acm2
vo1 vo 2
RD
RD


1
vicm vicm
2 Rss
 2 Rss
gm
 Output taken differentially
vo 2 - vo1
Acm 
0
vicm
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Common-Mode Rejection Ratio
• Common-mode rejection ratio(CMRR)
 Output taken single-ended
Ad 1
Ad 2
CMRR 

 g m Rss
Acm1
Acm2
 Output taken differentially
CMRR  
This is true only when the circuit is perfectly matched.
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Mismatch on CMRR
• Effect of RD mismatch on CMRR
vo  vo 2 - vo1  -
RD
vicm
2 Rss
CMRR  (2 g m Rss ) (
RD
)
RD
• Effect of gm mismatch on CMRR
CMRR  (2 g m Rss ) (
g m
)
gm
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Mismatch on CMRR
Determine the common-mode gain
resulting from a mismatch in the gm
values of Q1 and Q2.
Common-mode half circuit is not
available due to mismatch in circuit.
The nominal value gm.
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Mismatch on CMRR
• Effect of gm mismatch on CMRR
id 1
g m1

id 2
gm2
vs  vicm
id 1 - id 2 
g m vicm
2 g m Rss
CMRR  (2 g m Rss ) (
g m
)
gm
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The BJT Differential Pair
• Basic operation
• Large-signal operation
• Small-signal operation
 Differential gain
 Common-mode gain
 Common-mode rejection ration
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The BJT Differential Pair
The basic BJT differential-pair configuration.
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Basic Operation
The differential pair with a commonmode input signal vCM.
Two transistors are matched.
Current source with infinite output
resistance.
Current I divide equally between two
transistors.
The difference in voltage between the
two collector is zero.
The differential pair rejects the
common-mode input signal as long as
two transistors remain in active region.
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Basic Operation
The differential pair with a
“large” differential input signal.
Q1 is on and Q2 is off.
Current I entirely flows in Q1.
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Basic Operation
The differential pair with a
large differential input signal of
polarity opposite to that in (b).
Q2 is on and Q1 is off.
Current I entirely flows in Q2.
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Basic Operation
The differential pair with a
small differential input signal vi.
Small signal operation or
linear amplifier.
Assuming the bias current
source I to be ideal and thus I
remains constant with the
change in vCM.
Increment in Q1 and
decrement in Q2.
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Large-Signal Operation
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Large-Signal Operation
• Nonlinear curves.
• Linear segments.
• Maximum value of input differential voltages
vid  12 VT
vid  4VT  100mv
• Enlarge the linear segment by including equal resistance Re
in series with the emitters.
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Large-Signal Operation
The transfer characteristics of the BJT differential pair (a) can be linearized
by including resistances in the emitters.
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Small Signal Operation
The currents and voltages in the differential amplifier when a small
differential input signal vid is applied.
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Small Signal Operation
A simple technique for determining the signal currents in a differential amplifier
excited by a differential voltage signal vid; dc quantities are not shown.
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Small Signal Operation
A differential amplifier
with emitter resistances.
Only signal quantities
are shown (in color).
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Input Differential Resistance
• Input differential resistance is finite.
Rid 
vid
 (1   )2re  2r
ib
The resistance seen between the two bases is equal to the
total resistance in the emitter circuit multiplied by (1+β).
• Input differential resistance of differential pair with emitter
resistors.
vid
Rid 
 (1  （
) 2re＋2 Re )
ib
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Differential Voltage Gain
• Differential voltage gain
 Output voltage taken single-ended
vo1
Ad 1 
 - 12 g m RC
vid
vo 2 1
Ad 2 
 2 g m RC
vid
 Output voltage taken differentially
Ad 
vo 2 - vo1
 g m RC
vid
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Differential Voltage Gain
• Differential voltage gain of the differential pair with
resistances in the emitter leads
 Output voltage taken single-ended
vo1
1 RC
Ad 1 
vid
2 re  Re
vo 2 1 RC
Ad 2 

vid 2 re  Re
 Output voltage taken differentially
vo 2 - vo1
RC
Ad 

vid
re  Re
The voltage gain is equal to the ratio of the total resistance
in the collector circuit to the total resistance in the
emitter circuit.
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Differential Half-Circuit Analysis
Differential input signals.
Single voltage at joint
emitters is zero.
The circuit is symmetric.
Equivalent commonemitter amplifiers in (b).
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Differential Half-Circuit Analysis
This equivalence applies only
for differential input signals.
Either of the two commonemitter amplifiers can be used to
find the differential gain,
differential input resistance,
frequency response, and so on,
of the differential amplifier.
Half circuit is biased at I/2.
The voltage gain(with the
output taken differentially) is
equal to the voltage of half
circuit.
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Differential Half-Circuit Analysis
The differential amplifier fed
in a single-ended fashion.
Signal voltage at the emitter is
not zero.
Almost identical to the
symmetric one.
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Common-Mode Gain
The differential amplifier fed by a common-mode voltage signal vicm.
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Common-Mode Gain
Equivalent “half-circuits” for common-mode calculations.
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Common-Mode Gain
• Common-mode voltage gain
 Output voltage taken single-ended
vo1
RC
Acm1 
vicm
2 REE
Acm2
vo 2
RC

vicm
2 REE
 Output voltage taken differentially
v -v
Acm  o 2 o1  0
vid
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Common-Mode Rejection Ratio
• Common-mode rejection ratio
 Output voltage taken single-ended
CMRR  g m REE
 Output voltage taken differentially
CMRR  
This is true only when the circuit is symmetric.
• Mismatch on CMRR
RC RC
Acm 
2 REE RC
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Input Common-Mode Resistance
Definition of the input common-mode resistance Ricm.
The equivalent common-mode half-circuit.
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Input Common-Mode Resistance
• Input common-mode resistance
2Ricm  (1   )(2REE // ro )
Ricm  (1   )( REE //
ro
)
2
• Input common-mode resistance is very large.
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Example
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Example (cont’d)
•
•
•
•
•
Evaluate the following:
The input differential resistance.
The overall differential voltage gain(neglect the
effect of ro).
The worst-case common-mode gain if the two
collector resistance are accurate within ±1%.
The CMRR, in dB.
The input common-mode resistance(suppose the
Early voltage is 100V).
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The Differential Amplifier with
Active Load
• Replace resistance RD with a constant current
source results in a much high voltage gain as
well as saving in chip area.
• Convert the output from differential to
single-ended.
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Differential-to-Single-Ended
Conversion
A simple but inefficient approach for differential to
single-ended conversion.
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The Active-Loaded MOS
Differential Pair
The active-loaded MOS differential pair.
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The Active-Loaded MOS
Differential Pair
The circuit at equilibrium assuming perfect matching.
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The Active-Loaded MOS
Differential Pair
The circuit with a differential input signal applied, neglecting
the ro of all transistors.
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Differential Gain of the ActiveLoaded MOS Pair
• The output resistance ro plays a significant
role in the operation of active-loaded
amplifier.
• Asymmetric circuit.
• Half-circuit is not available.
• The gain will be determined as GmRo
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Short-Circuit Transconductance
Determining the short-circuit transconductance Gm = io/vid
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Short-Circuit Transconductance
Gm  g m
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Output Resistance
Circuit for determining Ro. The circled numbers
indicate the order of the analysis steps.
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Output Resistance
Circuit for
determining Ro.
The circled numbers
indicate the order of
the analysis steps.
Ro  ro 2 // ro 4
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Differential Gain
• The differential gain is determined as GmRo
Ad  Gm Ro  gm (ro2 // ro4）
• When
ro 2  ro 4  ro
A0
Ad  g m ro 
2
1
2
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Common-Mode Gain and CMRR
Analysis of the activeloaded MOS differential
amplifier to determine its
common-mode gain.
Power supplies
eliminated.
Rss is the output resistance
of the current source.
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Common-Mode Gain and CMRR
Asymmetric circuit.
Each of the two transistors
as a CS configuration with a
large source degeneration
resistance 2Rss.
Common-mode gain:
ro 4
1
1
Acm  2 Rss 1  g m3r03
2 g m3 Rss
CMRR
CMRR  ( g m ro )(g m Rss )
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The Bipolar Differential Pair with
Active Load
Active-loaded bipolar differential pair.
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Determine the Transconductance
Gm  g m
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Determine the output Resistance
Ro  ro 2 // ro 4
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Differential Gain
• The differential gain is determined as GmRo
Ad  Gm Ro  gm (ro2 // ro4）
• When
ro 2  ro 4  ro
A0
Ad  g m ro 
2
1
2
• Input differential resistance
Rid  2r
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Common-Mode Gain and CMRR
Common-mode gain:
Acm  -
ro 4 2
r
 - o4
2 REE 3
3 REE
CMRR
CMRR  ( g m r02 // ro 4 )(
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3 REE
ro 4
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)
Frequency Response of the
Resistively Loaded MOS Amplifier
A resistively loaded MOS
differential pair with the transistor
supplying the bias current
explicitly shown.
It is assumed that the total
impedance between node S and
ground, ZSS, consists of a
resistance RSS in parallel with a
capacitance CSS.
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Frequency Response of the
Resistively Loaded MOS Amplifier
(b) Differential half-circuit. (c) Common-mode half-circuit.
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Frequency Response of the
Resistively Loaded MOS Amplifier
common-mode gain
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Frequency Response of the
Resistively Loaded MOS Amplifier
Differential Gain
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Frequency Response of the
Resistively Loaded MOS Amplifier
CMRR with frequency.
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Multistage Amplifier
• A four-stage bipolar op amplifier
• A two-stage CMOS op amplifier
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Multistage Amplifier
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Multistage Amplifier
• The first stage(input stage) is differential-in,
differential-out and consists of Q1 and Q2.
• The second stage is differential-in, single-ended-out
amplifier which consists of Q3 and Q4.
• The third stage is CE amplifier which consists of
pnp transistor Q7 to shifting the dc level.
• The last stage is the emitter follower.
• Biasing stage.
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Multistage Amplifier
Equivalent circuit for calculating
the gain of the input stage of the
example.
Input differential resistance
Rid  2r 1  20.2k
Gain of first stage
v01 Ri 2 //( R1  R2 )
A1 

 22.4
vid
re1  re 2
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Multistage Amplifier
Equivalent circuit for calculating
the gain of the second stage of
the example.
Gain of second stage
v02
Ri 3 // R3
A2 
 -59.2
v01
re 4  re5
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Multistage Amplifier
Equivalent circuit for calculating the
gain of the third stage of the example.
Gain of third stage
v03
Ri 4 // R5
A3 
 -6.42
v02
re7  R4
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Multistage Amplifier
Equivalent circuit for calculating the
gain of the output stage of the example.
Gain of output stage
v0
R6
A4 
 0.998
v03
re8  R6
Output resistance
Ro  R6 //re8  R5 (1   )  152
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Two-Stage CMOS Op-Amp
Configuration
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