Transcript Semiconductor Manufacturing Technology

Semiconductor
Manufacturing Technology
Michael Quirk & Julian Serda
© October 2001 by Prentice Hall
Chapter 9
IC Fabrication Process
Overview
Semiconductor Manufacturing Technology
by Michael Quirk and Julian Serda
© 2001 by Prentice Hall
Major Fabrication Steps in MOS Process Flow
UV light
Mask
oxygen
exposed
photoresist
photoresist
Silicon dioxide
oxide
Silicon substrate
Oxidation
(Field oxide)
Exposed
Photoresist
Mask-Wafer
Photoresist
Coating
Alignment and Exposure
Dopant gas
Ionized CF4 gas
photoresist
oxide
Ionized oxygen gas
oxide
oxygen
gate oxide
Oxide
Etch
Photoresist
Strip
Oxidation
(Gate oxide)
Photoresist
Develop
Ionized CCl4 gas
Silane gas
polysilicon
Polysilicon
Deposition
oxide
Polysilicon
Mask and Etch
Scanning
ion beam
silicon nitride
top nitride
G
ox
S
Contact
holes
D
Ion
Implantation
S
G
D
Active
Regions
S
G
D
Nitride
Deposition
S G D
Contact
Etch
Used with permission from Advanced Micro Devices
Semiconductor Manufacturing Technology
by Michael Quirk and Julian Serda
Figure 9.1
Metal
contacts
G
drain
D
S
Metal
Deposition and
Etch
© 2001 by Prentice Hall
CMOS Process Flow
• Overview of Areas in a Wafer Fab
–
–
–
–
–
–
Diffusion
Photolithography
Etch
Ion Implant
Thin Films
Polish
• CMOS Manufacturing Steps
• Parametric Testing
Semiconductor Manufacturing Technology
by Michael Quirk and Julian Serda
© 2001 by Prentice Hall
Model of Typical Wafer Flow
in a Sub-Micron CMOS IC Fab
Wafer Fabrication (front-end)
Wafer Start
Unpatterned
Wafer
Diffusion
Completed Wafer
Test/Sort
Thin Films
Polish
Photo
Etch
Implant
Used with permission from Advanced Micro Devices
Semiconductor Manufacturing Technology
by Michael Quirk and Julian Serda
Figure 9.2
© 2001 by Prentice Hall
CMOS Manufacturing Steps
1. Twin-well Implants
14
Passivation layer
2. Shallow Trench Isolation
Bonding pad metal
ILD-6
3. Gate Structure
ILD-5
4. Lightly Doped Drain Implants
M-4
13
5. Sidewall Spacer
ILD-4
M-3
6. Source/Drain Implants
ILD-3
12
7. Contact Formation
M-2
11
8. Local Interconnect
ILD-2
M-1
9. Interlayer Dielectric to Via-1
Via
10. First Metal Layer
11. Second ILD to Via-2
12. Second Metal Layer to Via-3
13. Metal-3 to Pad Etch
ILD-1
9
Poly gate
8
LI metal
n+
2
7
10
3
p+
4
5
LI oxide
p+
STI
n-well
n+
n+
p+
6
p-well
1
p- Epitaxial layer
14. Parametric Testing
p+ Silicon substrate
Semiconductor Manufacturing Technology
by Michael Quirk and Julian Serda
© 2001 by Prentice Hall
n-well Formation
Phosphorus implant
Thin
Films
2
Polish
3
5
Photoresist
2
1
Diffusion
3
Photo
Etch
4
Oxide
4
n-well
5
~5 um
1
Implant
p- Epitaxial layer
p+ Silicon substrate
Semiconductor Manufacturing Technology
by Michael Quirk and Julian Serda
Figure 9.8
(Dia = 200 mm, ~2 mm thick)
© 2001 by Prentice Hall
p-well Formation
Boron implant
Thin
Films
Polish
1
Photoresist
1
Diffusion
3
Photo
Etch
Oxide
n-well
2
2
p-well
3
p- Epitaxial layer
Implant
p+ Silicon substrate
Semiconductor Manufacturing Technology
by Michael Quirk and Julian Serda
Figure 9.9
© 2001 by Prentice Hall
STI Trench Etch
Selective etching opens isolation regions in the epi layer.
+Ions
Thin
Films
1
2
Diffusion
3
Photo
3
Polish
4
Etch
Photoresist
2
Nitride
1
Oxide
n-well
4
p-well
STI trench
p- Epitaxial layer
Implant
p+ Silicon substrate
Semiconductor Manufacturing Technology
by Michael Quirk and Julian Serda
Figure 9.10
© 2001 by Prentice Hall
STI Oxide Fill
Trench fill by chemical vapor deposition
Oxide
2
Thin
Films
2
Polish
Trench CVD oxide
Nitride
1
Diffusion
Photo
Etch
1
p-well
n-well
Liner oxide
p- Epitaxial layer
Implant
p+ Silicon substrate
Semiconductor Manufacturing Technology
by Michael Quirk and Julian Serda
Figure 9.11
© 2001 by Prentice Hall
STI Formation
Planarization by chemical-mechanical polishing
1
1
Thin
Films
Polish
Photo
Etch
STI oxide after polish
2
Nitride strip
2
Diffusion
p-well
n-well
Liner oxide
p- Epitaxial layer
Implant
p+ Silicon substrate
Semiconductor Manufacturing Technology
by Michael Quirk and Julian Serda
Figure 9.12
© 2001 by Prentice Hall
Poly Gate Structure Process
3
Thin
Films
1
2
Diffusion
3
Photo
Polish
4
Etch
Polysilicon
deposition
1
Photoresist
ARC
2
4
Poly gate etch
Gate oxide
p-well
n-well
p- Epitaxial layer
Implant
p+ Silicon substrate
Semiconductor Manufacturing Technology
by Michael Quirk and Julian Serda
Figure 9.13
© 2001 by Prentice Hall
n- LDD Implant
2
Thin
Films
Polish
Photo
Etch
1
Arsenic n- LDD implant
Photoresist mask
1
Diffusion
n-
n-well
n-
n-
p-well
2
p- Epitaxial layer
Implant
p+ Silicon substrate
Semiconductor Manufacturing Technology
by Michael Quirk and Julian Serda
Figure 9.14
© 2001 by Prentice Hall
p- LDD Implant
2
Thin
Films
Polish
Photo
Etch
BF2 p- LDD implant
1
Photoresist Mask
mask
1Photoresist
1
Diffusion
n-
p-
p-
n-well
n-
n-
p-well
p-
2
p- Epitaxial layer
Implant
p+ Silicon substrate
Semiconductor Manufacturing Technology
by Michael Quirk and Julian Serda
Figure 9.15
© 2001 by Prentice Hall
Side Wall Spacer Formation
2
1
Thin
Films
Spacer etchback by anisotropic plasma etcher
Polish
1
+Ions
Spacer oxide
Side wall spacer
2
Diffusion
Photo
Etch
n-
p-
p-
n-well
n-
n-
p-well
p-
p- Epitaxial layer
Implant
p+ Silicon substrate
Semiconductor Manufacturing Technology
by Michael Quirk and Julian Serda
Figure 9.16
© 2001 by Prentice Hall
n+ Source/Drain Implant
2
Thin
Films
Polish
Photo
Etch
1
Arsenic n+ S/D implant
Photoresist mask
1
Diffusion
n+
n-well
n+
p-well
n+
2
p- Epitaxial layer
Implant
p+ Silicon substrate
Semiconductor Manufacturing Technology
by Michael Quirk and Julian Serda
Figure 9.17
© 2001 by Prentice Hall
p+ Source/Drain Implant
2
Thin
Films
Polish
Photo
Etch
Boron p+ S/D implant
1
Photoresist Mask
mask
1Photoresist
1
Diffusion
3
n+
p+ n-well
p+
n+ p-well
n+
p+
2
p- Epitaxial layer
Implant
p+ Silicon substrate
Semiconductor Manufacturing Technology
by Michael Quirk and Julian Serda
Figure 9.18
© 2001 by Prentice Hall
Contact Formation
1
1
2
3
Thin
Films
Polish
Titanium depostion
2
Titanium etch
Tisilicide contact formation (anneal)
3
Diffusion
Photo
Etch
n+
p+ n-well
p+
n+
p-well
n+
p+
p- Epitaxial layer
Implant
p+ Silicon substrate
Semiconductor Manufacturing Technology
by Michael Quirk and Julian Serda
Figure 9.19
© 2001 by Prentice Hall
LI Oxide as a Dielectric for Inlaid LI Metal
(Damascene)
LI metal
LI oxide
Semiconductor Manufacturing Technology
by Michael Quirk and Julian Serda
Figure 9.20
© 2001 by Prentice Hall
LI Oxide Dielectric Formation
2 Doped oxide CVD
3
2
1
Thin
Films
1 Nitride CVD
3 Oxide polish
Polish
4 LI oxide etch
LI oxide
4
Diffusion
Photo
Etch
p-well
p-well
p- Epitaxial layer
Implant
p+ Silicon substrate
Semiconductor Manufacturing Technology
by Michael Quirk and Julian Serda
Figure 9.21
© 2001 by Prentice Hall
LI Metal Formation
1
Diffusion
2
3
4
Thin
Films
Polish
Photo
Etch
Ti/TiN
2 deposition
3 Tungsten
deposition
4 LI tungsten polish
LI oxide
1
Ti deposition
p-well
n-well
p- Epitaxial layer
Implant
p+ Silicon substrate
Semiconductor Manufacturing Technology
by Michael Quirk and Julian Serda
Figure 9.22
© 2001 by Prentice Hall
Via-1 Formation
1 ILD-1 oxide
deposition
2 Oxide polish
2
1
Thin
Films
ILD-1 oxide etch
3 (Via-1 formation)
ILD-1
Polish
LI oxide
3
Diffusion
Photo
Etch
p-well
n-well
p- Epitaxial layer
Implant
p+ Silicon substrate
Semiconductor Manufacturing Technology
by Michael Quirk and Julian Serda
Figure 9.23
© 2001 by Prentice Hall
Plug-1 Formation
Ti/TiN
2 deposition
1
Diffusion
2
3
4
Thin
Films
Polish
Photo
Etch
3 Tungsten
deposition
1
Ti dep.
4 Tungsten polish (Plug-1)
ILD-1
LI oxide
p-well
n-well
p- Epitaxial layer
Implant
p+ Silicon substrate
Semiconductor Manufacturing Technology
by Michael Quirk and Julian Serda
Figure 9.24
© 2001 by Prentice Hall
SEM Micrographs of Polysilicon,
Tungsten LI and Tungsten Plugs
Tungsten LI
Polysilicon
Tungsten
plug
Mag. 17,000 X
Micrograph courtesy of Integrated Circuit Engineering
Semiconductor Manufacturing Technology
by Michael Quirk and Julian Serda
Photo 9.4
© 2001 by Prentice Hall
Metal-1 Interconnect Formation
Ti Deposition
1
1
2
Al + Cu (1%)
2 deposition
3
3
TiN
deposition
4 Metal-1 etch
ILD-1
Thin
Films
Polish
LI oxide
4
Diffusion
Photo
Etch
p-well
n-well
p- Epitaxial layer
Implant
p+ Silicon substrate
Semiconductor Manufacturing Technology
by Michael Quirk and Julian Serda
Figure 9.25
© 2001 by Prentice Hall
SEM Micrographs of First Metal Layer
over First Set of Tungsten Vias
TiN metal cap
Metal 1, Al
Tungsten
plug
Mag. 17,000 X
Micrograph courtesy of Integrated Circuit Engineering
Semiconductor Manufacturing Technology
by Michael Quirk and Julian Serda
Photo 9.5
© 2001 by Prentice Hall
Via-2 Formation
2
ILD-2 oxide
deposition
ILD-2 oxide etch
4 (Via-2 formation)
3 Oxide polish
1 ILD-2 gap fill
1 2
Thin
Films
3
ILD-1
Polish
LI oxide
4
Diffusion
Photo
Etch
p-well
n-well
p- Epitaxial layer
Implant
p+ Silicon substrate
Semiconductor Manufacturing Technology
by Michael Quirk and Julian Serda
Figure 9.26
© 2001 by Prentice Hall
Plug-2 Formation
Ti/TiN
2 deposition
1 Ti deposition
1
Diffusion
2
3
4
Thin
Films
Polish
Photo
Etch
Tungsten
deposition 3
(Plug-2)
Tungsten
4 polish
ILD-2
ILD-1
LI oxide
p-well
n-well
p- Epitaxial layer
Implant
p+ Silicon substrate
Semiconductor Manufacturing Technology
by Michael Quirk and Julian Serda
Figure 9.27
© 2001 by Prentice Hall
Metal-2 Interconnect Formation
ILD-3 oxide
3 polish
Metal-2 deposition
1 to etch
2 Gap fill
4 Via-3/Plug-3 formation
ILD-3
ILD-2
ILD-1
LI oxide
p-well
n-well
p- Epitaxial layer
p+ Silicon substrate
Semiconductor Manufacturing Technology
by Michael Quirk and Julian Serda
Figure 9.28
© 2001 by Prentice Hall
Full 0.18 mm CMOS Cross Section
Passivation layer
Bonding pad metal
ILD-6
ILD-5
M-4
ILD-4
M-3
ILD-3
M-2
ILD-2
M-1
Via
ILD-1
Poly gate
LI oxide
LI metal
n+
p+
p+
STI
n-well
n+
n+
p+
p-well
p- Epitaxial layer
p+ Silicon substrate
Semiconductor Manufacturing Technology
by Michael Quirk and Julian Serda
Figure 9.29
© 2001 by Prentice Hall
SEM Micrograph of Cross-section of AMD
Microprocessor
Mag. 18,250 X
Micrograph courtesy of Integrated Circuit Engineering
Semiconductor Manufacturing Technology
by Michael Quirk and Julian Serda
Photo 9.6
© 2001 by Prentice Hall
Wafer Electrical Test using a Micromanipulator Prober
(Parametric Testing)
Photo courtesy of Advanced Micro Devices
Semiconductor Manufacturing Technology
by Michael Quirk and Julian Serda
Photo 9.7
© 2001 by Prentice Hall