Transcript Document
Low Power Wireless Design Dr. Ahmad Bahai National Semiconductor New paradigm in Wireless Power Efficiency J/Bits/s/Hz Bits/s/Hz Configurability Design for worst case Configurable Design Architecture Centralized Hybrid Power efficiency Distance to IP Network TX Power Data Rate Cellular Miles 100 mW 100s kbps WLAN Yards 10 mW 10s mbps UWB Feet mW 100s mbps Pervasive IP Tx power ~ Circuit power (1nJ/bit transmission energy- 10 m distance) Power = Tx power + Circuit power Comm Theory, Asym Values Eb 2C / W 1 lim ln 2 1.59dB C / W 0 N0 C /W Absolute minimum energy for reliable transmission of 1 bit of information Eb 691017.4 J Min switching energy for digital gate (1 electron @100mV): 1.6X10-20 C Pav Pav log2 e N0 N 0 ln 2 b/s Transmission vs. Circuit Energy Communication Theory usually considers Transmission energy only! Transmission Energy Spectral Efficiency R L CE B BTon But Ec Ton Optimal Bandwidth-time pair? Total Energy (MQAM) Platform Phy Tx/RX MAC layer including ARM and PCI PCI interface RF/Analog supporting up to 4 radios Power profile in WLAN (TX) DSP+MAC DAC BBFE LO RF FE PA 261, 22% 530, 44% 40, 3% 36, 3% 47, 4% 288, 24% Power profile in WLAN (RX) DSP+MAC ADC 174, 24% BBFE LO RF FE 176, 24% 60, 8% 47, 6% 200, 28% 72, 10% FEC Channel Effect IMEC Collaboration Comm Theory Approach Bandwidth SiNR Power Mask Dynamic Range Modulation Interference Margin Coding Data rate Noise figure Statistical performance Synchronization MAC State machines BER Channel Energy QoS Adaptive design Energy and Throughput Common Approach: Define SINR and capacity as Pl Gll Rl log Pj Glj nl j l , l 1,, L Assume BPSK with BER target of 10e-q, bandwidth W and target data rate of R>C; then we can show that minimal power vector supporting network topology for low SIR can be derived as: P ( I F ) 1 b P ( P1 , , PL ) Cl nl bl GllW / 2 q log 2 10 F Glk Cl G W ll 0 if k l if k l Design Strategy System level approach to low power communication design Case study: ZigBee •Profile the power consumption •Study effect of multi-layer optimization •A new design strategy IEEE 802.15.4 PHY BAND 2.4 GHz ISM 868 MHz 915 MHz ISM COVERAGE DATA RATE CHANNEL(S) Worldwide 250 kbps 16 Europe 20 kbps 1 Americas 40 kbps 10 Direct Sequence Spread Spectrum (DSSS) radio 2Mchip/s OQPSK modulation 1 symbol = 32-chip PN sequence 1 symbol = 4 bits PHY data rate: 250kbps Transmit power up to 0 dBm 802.15.4 spec. summary Symbol rate and Tx RF accuracy: +/- 40 ppm Packet Error Rate (PER) Defined for PSDU of 20x8 bits Sensitivity: -85 dBm (PER < 1%) RSSI: sens. level +10 dB, 40 dB range (+/- 6dB) Max input level: -20 dBm Jamming resistance (interference performance) 0 dB for adjacent channels (ref: -82 dBm) 30 dB for alternate channels (ref: -82 dBm) Interferer is 802.15.4 compliant interferer Tx Error Vector Magnitude : < 35% for 1000 chips Tx PSD: -20 dB or –30 dBm |f-Fc| > 3.5 MHz (rbw 100kHz) Output power: > -3 dBm (@ max power setting) Rx-Tx turnaround time: 12 Symbols (192 ms) ZBIC, one-chip solution ZBIC Power Profile 4-state/Transition Energy Profile VDD = 1.8V Shutdown 80 nA 970 us 691pJ 194 us 6.63 uJ Idle 396 uA 194 us 6.63 uJ RX 19.6 mA Transition Energy T(transition) x I(target state) x VDD TX -25 dBm: 8.42 mA -15 dBm: 9.71 mA -10 dBm: 10.9 mA -7 dBm: 12.17 mA -5 dBm: 12.27 mA -3 dBm: 14.63 mA -1 dBm: 15.785 mA 0 dBm: 17.04 mA IMEC/MIT Observations Efficiency (energy/bit) changes with: Larger packet size Transmit power control Network Load Contention Channel Coding Link layer performance Power Breakdown Breakdown between the states In high load, the node spends more time in RX than in TX mode! IMEC/MIT More comprehensive Energy model Energy efficiency metric: E[ Energytotal ] E[ Payload] E[ Energytotal ] k [ Energyt 0tal | statek ]P[statek ] TX, RX, Collision, sensing, Transitions, ramp up New model for total energy was used to optimize back off strategy in an ad-hoc network. Energy Efficient Backoff r W 1 L 1 W 1 1 N 1 L 1 W Standard backoff Proposed backoff Resetting back-off is more energy efficient than DCF backoff due to carrier sensing overhead. Summary Statistical Performance Analysis: New design paradigm in communication Configurable and low power design: Key Design objectives Multimode/Multi-layer Optimization Analog/mixed signal: critical in power consumption Mixed signal processing and cross layer optimization