Transcript AGENDA - Niels Bohr Institute

Forward Multiplicity Detector
(status and progress)
ALICE Si-FMD
Si-FMD (Forward Multiplicity Detector)
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Si-strip Ring counters (5) with 50.000 channels
-5.1<  < -1.7; 1.7<  < 3.4
Off-line charged particle multiplicity for A+A, p+p
Fluctuations event-by-event, flow analysis
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Geometry and integration defined.Prototyping of mech. Supports.
Final Si-sensor design ongoing.
Read out chain (FEE-BEE-DAQ) defined.Prototyping ongoing.
Performance/simulations
TDR in preparation.
o Concerns: ’ambient’ temperature, material
10/09 2003
Jens Jørgen Gaardhøje, NBI, [email protected]
1
ALICE Si-FMD
Si-FMD
Si3
Si2
Si1
 5 Si-strip rings segmented into
50.000 channels
 Rapidity coverage from ITS
(1.7) to 5.1.
 Segmentation sufficient for
‘Poisson’ analysis
• Main Off-line charged particle
multiplicity studies
• Average multiplicity (entropy,
stopping)
• Fluctuations (phase transitions)
• Flow (thermalisation,
hydrodynamics)
10/09 2003
Jens Jørgen Gaardhøje, NBI, [email protected]
2
Forward rapidity physics
at LHC
ALICE Si-FMD
BRAHMS@ RHIC snn= 200AGeV
pp
Plateau at LHC –6<<+6 ?
10/09 2003
Jens Jørgen Gaardhøje, NBI, [email protected]
3
ALICE Si-FMD
CERN Maquette 1:1
ITS-pixels
T0-R
Si1(outer)
V0-R
Si1 (inner)
Absorber
10/09 2003
Jens Jørgen Gaardhøje, NBI, [email protected]
4
Mechanical Installation
10/09 2003
ALICE Si-FMD
Jens Jørgen Gaardhøje, NBI, [email protected]
5
FMD Cabling on muon
side
ALICE Si-FMD
Digitized signals ,
HV and control
10/09 2003
Jens Jørgen Gaardhøje, NBI, [email protected]
6
Si1 mechanics model 1:1
ALICE Si-FMD
Outer ring not shown
Beam pipe support ring
Si detectors
Support plate
Engineering
study in
progress to
minimize
material,
maximize
rigidity
Digitizer card
10/09 2003
Jens Jørgen Gaardhøje, NBI, [email protected]
7
Heat dissipation
ALICE Si-FMD
 Heat dissipated by FE electronics of one
Si detector ring:
VA1’’ preamp chip (128 channels): 235 mW
 80 chips = 19 W / ring
Read-out electronics and power distribution:
 5 W/ring
Cooling: air flow between Si detector and
support plate radiation from VA chips to
support.
active (water) cooling of support plate is
considered
Detailed cooling studies (simulations of heat
profile) need to be done.
10/09 2003
Presently, the
temperature at the
FMD, T0, V0
location is >70 deg.
due to ITS heat
dissipation.
Effective general
cooling of this region
required !
Jens Jørgen Gaardhøje, NBI, [email protected]
8
Left Side: Si2 & Si3
ALICE Si-FMD
Details of mounting to be finalized
10/09 2003
Jens Jørgen Gaardhøje, NBI, [email protected]
9
Si rings manufactured
of 6” wafers
256
ALICE Si-FMD
Inner:
Rin=4.2 cm
Rout=17.2 cm
Outer:
Rin=15.4 cm
Rout=28.4 cm
512
Possible suppliers:
Micron, UK
Hamamatsu, JP
10x2x512=10240
20x2x256=10240
10/09 2003
Jens Jørgen Gaardhøje, NBI, [email protected]
10
Coverage in
pseudorapidity
ALICE Si-FMD
Design criteria:
Constraints:
Largest possible  coverage
Vacuum tube outer envelope: 42 mm,
Largest symmetry left and right
Outer radius, ITS, Absorber, cables
Overlap between systems
Background from secondaries(small angles)
Si1:
Out: 1.70< <2.29
In: 2.01< <3.40
Si2:
Out: -2.29<<-1.7
In: -3.68< <-2.28
Si3:
In: -5.09< <-3.68

10/09 2003
Jens Jørgen Gaardhøje, NBI, [email protected]
Vertex shift
(10cm): |d|  0.1
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Details of Si sensors
ALICE Si-FMD
Hamamatsu, Micron
10/09 2003
Jens Jørgen Gaardhøje, NBI, [email protected]
12
Adjusted acceptance
10/09 2003
ALICE Si-FMD
Jens Jørgen Gaardhøje, NBI, [email protected]
13
Hybrid with Viking PA
chips
Hybrid cards contain:
 FE–Preampl. chips
 Bias voltages distribution
 Gate/strobe distribution
 Read-out clock distribution
 Detector bias connection
ALICE Si-FMD
Connector(s) for
power, control, read-out
VA preamp+shaper: 128 ch
Si detector
10/09 2003
Jens Jørgen Gaardhøje, NBI, [email protected]
14
ALICE Si-FMD
FMD RO strategy
FMD Read-Out and Control Electronics
ON DETECTOR
IN
COUNTING
ROOM
IN CAVERN
FMD Segment
Analog serial link
(10 MHz)
 0.5 m
FMD Digitizer
Detector
Data Link
(50-60 m)
FMD RCU
CTRL
DDL - INT
ALTRO
Digital serial
links
(15-20 m)
CTRL
ALTRO
CTRL
BOARD
CTRL
TTC-RX
Slow-Control
Interface
ALTRO
Local
Controller
Data
receiver
Read-out CTRL
VA
1 ring: 10/20 segments
Full FMD: 70 segments
VA read-out
control
Slow control
& Trigger
Trigger &
Slow Ctrl
2 Digitizers
10 Digitizers
1 RCU per side
2 RCU’s
1 DDL per side
2 DDL’s
BSN, 21 Nov 2002
10/09 2003
Jens Jørgen Gaardhøje, NBI, [email protected]
15
Si-FMD electronics
overview
ALICE Si-FMD
SI-FMD channel count
Segments
(wafers)
Phi
sectors
Radial
strips
FE channels
VA chips
(128 ch/chip)
ALTRO
chips
FMD
Digitizers
FMD
RCU
Si1 inner
10
20
512
10,240
80
6
2
1
Si1 outer
20
40
256
10,240
80
6
2
Si2 inner
10
20
512
10,240
80
6
2
Si2 outer
20
40
256
10,240
80
6
2
Si3
10
20
512
10,240
80
6
2
Total
system
70
140
51,200
400
30
10
1
2
Note: We have increased the number of strips, but use more integrated FE chips –
red values are changed.
10/09 2003
Jens Jørgen Gaardhøje, NBI, [email protected]
16
ALICE Si-FMD
FMD FEE test setup
FMD FEE test
Ext trigger
ALTRO tester
Labview
DAQ
CTRL
Ext clock
ALTRO
Power
Biases
Si
detector
Clock
10 MHz
VA
CTRL
Trig in
NBI test board:
- generates trigger
+ pulse on Si det
- level adaption of
VA-to-ALTRO
- VA read-out clock
+ controls
- ALTRO digitization
clock (sync.)
BSN, 21 Nov 2002
10/09 2003
Jens Jørgen Gaardhøje, NBI, [email protected]
17
Si-FEE-Digitizer
prototyping at NBI
ALICE Si-FMD
DAQ/
Labview
Si-strip detector
+ VA’’ preamp
ALTRO tester
10/09 2003
VA’’ read-out controller
Jens Jørgen Gaardhøje, NBI, [email protected]
18
First prototype test
results
Output from VA chip:
(128 channels multiplexed
into serial read-out)
Note: 3 bad Si/VA channels
ALICE Si-FMD
Trigger
Si+
Preamp
Out
Output from ALTRO:
(128 time bins are digitized)
Note: general shape
+ 3 bad channels repeated
Altro Out
Noise still too high
Timing still not stable
10/09 2003
Jens Jørgen Gaardhøje, NBI, [email protected]
19
Control
room (ACR)
Slow Controls
Follow main strategy
FMD
ALICE Si-FMD
28/02/03
[FSM?]
Database(s)
PVSS II
PVSS II
OPC
client
User interface
PVSS II
DIM
client
DCS
Ethernet
PVSS II
PVSS II
OPS client
CAEN OPCserver
OPC client
CAEN OPCserver
DIMserver
OPC client
?
PCI-CAN?
PCI-CAN?
PCI-Profibus
PCI-CAN?
E
E
1
2
Ethernet is
considered
as alternative
1
Cavern
CAEN ?
C
DDL
CAEN ?
P
Counting room
PVSS II
2
FMD-RCU
TTC
(PCI? VME?)
P?
70
LV
140 LV
In magnet
HV
LVL
0
trig
10
20
300?
10
Detector
High
10/09
Voltage
Preamps
Preamps
2003
FMD
Digitizers
Digitizers
Crate Control NBI, [email protected]
Jens
Jørgen Gaardhøje,
20
Charged particle occupancy
including secondaries
x2
x2
Si-1 inner
Si-1 outer
1
ALICE Si-FMD
x2
Si-3
1
1
20  sectors
40  sectors
20  sectors
512 strips each
256 strips each
512 strips each
10240 channels
10240 channels
10240 channels
Have increased number of strips by factor of 2 using ’128 ch VA-prime’
PA chip at practically same cost => average occupancy <1 for most strips!
10/09 2003
Jens Jørgen Gaardhøje, NBI, [email protected]
21
Background from
Secondaries
ALICE Si-FMD
Si2 inner
Si1 inner
Si1 outer
Si3
Primaries
Beam pipe
ITS
T0,V0,Abs, frames
10/09 2003
Jens Jørgen Gaardhøje, NBI, [email protected]
22
Reconstruction of ’true’
multiplicity
1 HIJING event
ALICE Si-FMD
10 HIJING events
Input dist
and
reconstructed
Primaries+secondaries
Primaries
HijingGeant= R * Hijing
R = R() response matrix
10/09 2003
Jens Jørgen Gaardhøje, NBI, [email protected]
23
Iterative convolution of
trial spectrum
O = R * TrueSpec
ALICE Si-FMD
Test of flat input distribution
O(0)= R(0)* H
TrueSpec(1)=O/O(1)*H
O(1)= R(1)* TrueSpec(1)
…Continue until O(n)O
10/09 2003
Jens Jørgen Gaardhøje, NBI, [email protected]
24
Si-FMD timetable (1)
ALICE Si-FMD
A
FRONT END (FE) READ OUT ELECTRONICS
Completed
1
Demonstrate functionality of conceptual layout of FEE
(Viking PA chip, control system, interface to ALTRO test board)
August 2003
2
Final choice of VA pre-ampl. chip. RO test
3
Test FEE system coupled to sample Si detector. Source and
electron beam tests.
4
Design, construction and test of prototype FMD digitizer card
(FMDD), RO test with ’mini’ FMD-RCU
5
Full Si detector element + electronics chain RO with realistic
RCU and DDL link to DAQ.
June 1 , 2004
B
MECHANICS AND INTEGRATION
Completed
1
Full scale model manufactured (Si1)
February 1, 2003
2
Cabling and Cooling issues resolved
June 1, 2003
3
Full integration sequence decided
June 1, 2003
10/09 2003
Jens Jørgen Gaardhøje, NBI, [email protected]
25
Si-FMD timetable (2)
ALICE Si-FMD
C.
SILICON DETECTOR
Completed by
1
Complete market survey
May, 2003
2
Define final specs
October 2003
3
Place order for prototype with industry
November 2003
4
Delivery Si-wafer prototype
February 2004
5
Start production of Si-hybrid FEE card
December 2003
6
Delivery prototype hybrid
March 2004
7
Si prototype test with FEE and BEE test RO setup
April 2004
8
Place final order for Si with industry
October 2004
Pre-assembly test
July-Nov 2004
Construction, assembly , test at RHIC
2005
Installation
June-Sept 2006
10/09 2003
Jens Jørgen Gaardhøje, NBI, [email protected]
26
Si-FMD, TO,VO
TDR time table.
ALICE Si-FMD
 Fair amount of written material exists already
(T0 100 pgs, Si-FMD 50 pgs, V0 20 pgs)





April 15. Collect first detector chapters.
June ’03. Editorial meeting. 1rst draft.
Summer ’03 Si-FMD electronics chain test.
June ’03 T0 test beam
August ’03 V0 test beam
 TDR writing: fall 2003
10/09 2003
Jens Jørgen Gaardhøje, NBI, [email protected]
27
Techical Design Report
ALICE Si-FMD
Alice collab list.
(5pgs)
Summary of contents
(2pgs)
Table of contents. List of tables and figs.
(4pgs)
Color pictures of selected det. elements etc.
(6pgs)
1. Physics objectives and design considerations
T0, V0, Si-FMD trigger, timing, on-line mult, off-line mult, fluct,
bgd rejection, overall performance, coverage etc ...
(10
pgs)
2. Design objectives, mechanical structure, Integration
T0, V0, Si-FMD mounting, tolerances, clearances,
inst. seq., cooling, cabling ...
(10pgs)
3. T0
(40 pgs)
4. V0
(40 pgs)
5. Si-FMD
(40 pgs)
6. Installation, slow control, DAQ, safety.
(10
pgs)
7. Organization
(5 pgs)
Group org., construction, installation, cost
8. References.
(4pgs)
9. Index
(2 pgs)
(approx. 180 pgs)
10/09 2003
Jens Jørgen Gaardhøje, NBI, [email protected]
28
Tasks and decisions
for Weekly meetings (1)
ALICE Si-FMD
1) Si sensors:
- define final specs of sensor properties
- negotiate price again with Hamamatsu and Micron
- choose company
- order prototype
2) Voltage supplies
- define Voltage requirements (Volt, current, remote control and DCS)
- investigate market (check out ITS or other Si systems in ALICE)
3) Bonding
- decide on bonding strategy (CERN or other)
- make arrangement with bonder
4) FEE-preamplifier card.
- define final specs of FEE hybrid card
- define interface to ALTRO
-digitizer card and other slow controls.
- define strategy: home built hybrid card with VA-prime from IDEAS or
design and production by IDEAS and production for card?
-updated cost estimate for industrial design and production (IDEAS)
10/09 2003
Jens Jørgen Gaardhøje, NBI, [email protected]
29
Tasks and decisions
for Weekly meetings(2)
ALICE Si-FMD
5) Digitizer card (ALTRO board)
-define interface to FEE and RCU
- define necessary modifications to standard ALTRO boards
6) RCU card.
- define interface to digitizer card (ALTRO board)
- define necesary modifications to RCU
7) DDL and connection to DAQ
-define modifications needed, if any
8) cabling and services, cooling
- define cable types and length.
- define connectors
- define own cooling needs
- define placement of cards/DDL etc in ALICE
9) Mechanical
- define mechanical mounts for Si1, Si2, Si3.
10) Slow Control and DAQ communication
- define tasks to be done
-collect information and establish contact with DCS and DAQ groups.
10/09 2003
Jens Jørgen Gaardhøje, NBI, [email protected]
30
Extra’s
10/09 2003
ALICE Si-FMD
Jens Jørgen Gaardhøje, NBI, [email protected]
31
ALICE Si-FMD
Front end electronics
REQUIREMENTS:
Adapted for 5-25pF capacitance
(300m Si, 0.5 cm2: 25pF,
1MIP: 22.400 e-)
Dynamic range: 0-20 MIPS
Radiation hardness: >200kRad
Peaking time: 1-2 s
Low noise (good S/N)
High integration
Sample/hold and serial readout, 10 MHz clock
Moderate power consumption
Simple slow controls and power
reg.
Affordable cost
10/09 2003
VA1 prime 2 (Viking-IDEAS):
Input capacitance: < 30 pF
0-20 MIPs
>1MRad (0.35 m tech.)
1-3 s
475 e- at 25 pF => S/N 20:1
128
10 Mhz clock
1.3 mW/ch
Test system available
OK
Jens Jørgen Gaardhøje, NBI, [email protected]
32
Multiplicity resolution
10/09 2003
ALICE Si-FMD
Jens Jørgen Gaardhøje, NBI, [email protected]
33
Reconstructed multiplicity.
Average and width
ALICE Si-FMD
1.7
Background Subtracted
All hits reconstructed
3.4
10/09 2003
Jens Jørgen Gaardhøje, NBI, [email protected]
34
ALICE Si-FMD
Background
Si2inner
Si2outer
Si1outer
Si3
=1.73
10/09 2003
Si1inner
=1.31
=2.4
Jens Jørgen Gaardhøje, NBI, [email protected]
35