RC-113 Kim IEDM 2005..
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Transcript RC-113 Kim IEDM 2005..
Performance Evaluation
of 50 nm In0.7Ga0.3As HEMTs
For Beyond-CMOS Logic Applications
D.-H. Kim and J. A. del Alamo
MIT
J.-H. Lee and K.-S. Seo
Seoul National University
Sponsors: MARCO-MSD, TND
Acknowledgement: MBE Technology
IEDM
December 14, 2005
1
Contents
1. Introduction
2. Fabrication of InGaAs HEMTs
3. Characterization of InGaAs HEMTs
– Logic Parameters
– Scaling Limit
4. Benchmarking against Si MOSFETs
5. Conclusions
2
InGaAs HEMTs: beyond-the-roadmap logic
technology?
Acknowledgement : Robert Chau, Intel
3
InGaAs HEMTs for the past 20 years
Tremendous intrinsic potential of
InGaAs HEMT technology
600
Cutoff Frequency [GHz]
500
Ultra High-speed ICs based on
InGaAs HEMT Technology
Fujitsu (02, EDL)
UIUC (03, EL)
IBM (03, IPRM)
IBM (04, VLSI)
100 Gb/s MUX, NTT (IEDM-02)
400
III-V HEMT
300
160~215 GHz (20 dB), TRW (IRPM-02)
III-V HBT
200
SiGe HBT
180~205 GHz (14 dB), HRL (MGWL-01)
Si CMOS
100
0
1985
1990
1995
2000
2005
Year
What would it take for InGaAs HEMT to become mainstream logic
technology?
4
Epitaxial Layer Structure
n+ Cap
InGaAs, x = 0.53
20 nm
Stopper
InP
6 nm
Barrier
InAlAs, x = 0.52
8 nm
δ-doping
Si
-
Spacer
InAlAs, x = 0.52
3 nm
InGaAs, x = 0.53
3 nm
InGaAs, x = 0.7
8 nm
InGaAs, x = 0.53
4 nm
InAlAs, x = 0.52
500 nm
Channel
Buffer
3 Inch S. I. InP Substrate
Grown by Molecular Beam Epitaxy
Strain InGaAs Channel & InP Stopper
mn,hall = 11,200 cm2/V-sec
5
Fabrication of 50 nm InGaAs HEMTs
PMMA
Mesa
Copolymer
Ohmic
EBL & Recess
ZEP-520
SiNx
SiNx
Lg=50 nm
Schottky
6
EBL for 50 nm T-gate Fabrication
- Conventional Method Head
Exposure
PMMA
P(MMAMAA)
ZEP
Foot
Exposure
- Newly Proposed Method Foot
Exposure
ZEP
Head
Exposure
PMMA
P(MMAMAA)
ZEP
Minimum Lg = ~ 100 nm
Minimum Lg = 50 nm
7
Two-Step Recess Technology
Selective
Wet-Etching
ZEP
Ar-Based
RIE
SiNx
SiNx
Ar-Based
RIE
InGaAs
Two-Step Recess
- InGaAs Cap : Wet (Citric Acid)
- InP Stopper : Dry (Ar-RIE)
< Ref. : Suemitsu et al. (IEDM 1998) >
InP Etch-stopper
8
Optimization : Structure Variation
InGaAs
InP
Ti
InGaAs
InP
tins = 17 nm
B = 0.4 eV
InAlAs
InGaAs
InAlAs
tins = 11 nm
B = 0.6 eV
InGaAs
Ti/Pt/Au on InP : Type A
InGaAs
InP
InAlAs
Ti
Ti/Pt/Au on InAlAs : Type B
InGaAs
InP
Pt
tins = 11 nm
B = 0.7 eV
InGaAs
Pt/Ti/Au on InAlAs : Type C
InAlAs
Buried Pt
(PtAs4)
tins = 7 nm
B = 0.8 eV
InGaAs
Buried Pt on InAlAs : Type D
9
Output characteristics for InGaAs HEMTs
1000
1000
Ti on InP
Lg=50nm
800
Lg=50nm
VGS=-0.2V
Lg=100nm
800
Lg=150nm
Lg=100nm
Ti on InAlAs
VGS=0.2V
Lg=150nm
600
VGS=-0.6V
400
VGS=-0.8V
200
0
0.00
0.25
0.50
0.75
Lg=100nm
VGS=0V
400
VGS=-0.2V
1.00
0
0.00
1.25
VDS [V]
Lg=50nm
600
200
VGS=-1.0V
1000
800
IDS [mA/mm]
IDS [mA/mm]
VGS=-0.4V
VGS=-0.4V
0.25
VGS=0.3V
0.75
Buried Pt on
L =100nm
InAlAs
Lg=50nm
800
Lg=150nm
VGS=-0.1V
200
IDS [mA/mm]
IDS [mA/mm]
400
VGS=0.5V
g
VGS=0.3V
600
400
VGS=0.1V
200
VGS=-0.3V
0
0.00
1.25
Lg=150nm
VGS=0.1V
600
1.00
VDS [V]
1000
Pt on InAlAs
0.50
0.25
0.50
0.75
VDS [V]
1.00
1.25
VGS=-0.1V
0
0.00
0.25
0.50
0.75
VDS [V]
1.00
1.25
10
Gm characteristics for 50 nm InGaAs HEMTs
1600
Ti on InP
Ti on InAlAs
Pt on InAlAs
Buried Pt on InAlAs
GM [mS/mm]
1200
800
400
VDS = 0.5 V
0
-1.5
-1.0
-0.5
0.0
0.5
VGS [V]
Ti on InP
Ti on InAlAs
Pt on InAlAs
Buried Pt on InAlAs
tins [nm]
17
11
11
7
GM,max [S/mm]
1.1
1.3
1.3
1.5
11
Subthreshold characteristics for 50 nm
InGaAs HEMTs
3
10
2
VDS= 0.5 V
10
1
ID IG [mA/mm]
10
ID
0
10
-1
10
-2
10
-3
10
-4
10
Ti on InP
Ti on InAlAs
Pt on InAlAs
Buried Pt on InAlAs
IG
-5
10
-1.5
-1.0
-0.5
0.0
0.5
VGS [V]
B
tins
improvement in subthreshold characteristics
12
Evaluation Methodology
Methodology of Chau (T-Nano 2005)
VCC = 0.5 V
1000
ID [mA/mm]
100
ID [mA/mm]
10
ION
1
VCC
3
1 mA/mm
1
2
V
3 CC
0.1
0.01
IOFF
1E-3
VDS = VCC = 0.5 V
1E-4
-1.0
-0.5
VT
0.0
0.5
VGSV
[V]
GS
- VT at ID = 1 mA/mm & S = 1/Slope(VGS=VT, VDS=VCC)
- DIBL = [VT (VDS = VCC) - VT (VDS = 0.05)] / VCC - 0.05
2
- ION = ID (VGS = VT +
VCC, VDS = VCC)
3
1
- IOFF = ID (VGS = VT − VCC, VDS = VCC)
3
13
10
4
10
3
2
10
2
10
1
10
1
10
0
10
0
10
4
10
3
10
Ti on InP
Ti on InAlAs
ID [mA/mm]
ID [mA/mm]
DIBL, S & ION/IOFF for 50 nm InGaAs HEMTs
10
-1
-2
10
-2
10
-3
10
-3
10
-4
10
-4
10
-1
10
VCC = 0.05 / 0.5 V
-1.5
-1.0
-0.5
0.0
0.5
Pt on InAlAs
Buried Pt on InAlAs
VCC = 0.05 / 0.5 V
-1.5
-1.0
-0.5
0.0
0.5
VGS [V]
VGS [V]
VT [V]
DIBL [mV/V]
S [mV/dec]
ION/IOFF
Ti on InP
-1.1
300
200
63
Ti on InAlAs
-0.65
220
130
1 10 3
Pt on InAlAs
-0.55
180
100
7.2 10 3
Buried Pt on InAlAs
-0.20
160
86
1.7 10 4
14
fT Scaling
500
VDS = 0.5 V
450
400
fT [GHz]
350
CPGD
Record fT
(Fujitsu)
(de-embedded)
-1
RS & RD
300
250
Lg
(de-embedded)
Ti on InP
Ti on InAlAs
Pt on InAlAs
Buried Pt on InAlAs
200
50
100
150
200
Gate Length, Lg [nm]
Poor scalability of GM & GO due to short-channel effects
Impact of parasitics : RS & RD & CPDG
15
Contents
1. Introduction
2. Fabrication of InGaAs HEMTs
3. Characterization of InGaAs HEMTs
– Logic Parameters
– Scaling Limit
4. Benchmarking against Si MOSFETs
5. Conclusions
16
Subthreshold Slope
Subthreshold Slope [mV/dec]
160
Planar Si MOSFETs
(Vcc = 1 ~ 1.5 V)
140
120
100
80
Ti on InAlAs
Pt on InAlAs
Buried Pt
on InAlAs
(VCC= 0.5 V)
60
0
50
100
150
200
Gate Length [nm]
Buried Pt InGaAs HEMTs exhibits S equivalent to Si MOSFETs
< Ref. : Chau et al. (T-Nano 2005) >
17
fT – Power Tradeoff
Cutoff Frequency, f T [GHz]
400
Buried Pt on InAlAs
(VCC = 0.5 V)
300
Lg= 50 nm
Lg= 100 nm
200
2.2
13
100
Si NMOS
(Lg= 80 nm, VCC= 0.7 V)
0
1
10
2
10
3
10
Power Dissipation [mW/mm]
InGaAs HEMTs show low power & high speed characteristics!
< Ref. : Kuhn et al. (VLSI 2004) >
18
Dependency of Logic Parameters on VT
Methodology of Lundstrom (IEDM, 2004)
1
VCC
3
1000
2
VCC
3
ION / IOFF
ID [mA/mm]
1
IOFF’
0.1
10
4
10
3
10
2
10
1
Ti on InP
Ti on InAlAs
Pt on InAlAs
Buried Pt on InAlAs
10
5
Lg = 50 nm
ION’
100
ID [mA/mm]
10
0.01
1E-3
VT
VDS = VCC = 0.5 V
1E-4
-1.0
-0.5
VT’
0.0
VGSV[V]
GS
0
10
0.5 -0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
VT' - VT [V]
Varying VT definition maps tradeoff between ION/IOFF and CV/I
Useful to explore suitability of novel devices with non-optimized VT
19
GATE DELAY vs. ION/IOFF
Ti on InP
Ti on InAlAs
Pt on InAlAs
Buried Pt on InAlAs
Gate Delay [psec]
10
Lg = 50 nm
VT’ – VT < 0
1
VT = VT’ @ 1 mA/mm
VCC = 0.5 V
10
0
10
1
10
2
10
3
10
4
10
5
VT’ – VT > 0
ION/IOFF
Chau’s approach to gate delay:
(CGS + CGD)V , I
CV
=
ION
I
CC
ON
VCC
20
GATE DELAY vs. ION/IOFF
10
40 nm NMOSFET
200 nm InSb HEMT
50 nm InGaAs HEMT
Gate Delay [psec]
Gate Delay [psec]
10
InGaAs HEMT
(VCC = 0.5 V)
1
Si MOSFET
(VCC = 1.1 V)
InSb HEMT
(VCC = 0.5 V)
10
1
10
2
10
3
10
4
ION/IOFF
10
5
1
InSb HEMTs
(VCC = 0.5 V)
Si NMOSFETs
(VCC = 1.1~1.3 V)
0.1
0
10
10
1
InGaAs HEMTs
(VCC = 0.5 V)
10
2
10
3
Gate Length, Lg [nm]
For 50 nm InGaAs HEMTs, CV/I = 0.66 ps @ VCC = 0.5 V
< Ref. : Chau et al. (T-Nano 2005) >
21
Conclusions
•
Enhancing B and shrinking tins essential for good logic
performance of InGaAs HEMTs
•
•
Logic performance of 50 nm InGaAs HEMTs:
–
ION/IOFF > 104, S < 86 mV/dec, DIBL = 160 mV/V @ VCC = 0.5 V
–
For ION/IOFF = 104, gate delay < 1 ps @ VCC = 0.5 V
–
Comparable to state of the art MOSFETs
Future options of InGaAs HEMTs for logic application
–
E-mode operation, MIS structure & self-aligned scheme
22