Transcript The Serial Communication Interface (SCI)

The Serial Communication
Interface (SCI)
MC9S12-C32
Lecture L4.9
Reference
HCS12 Serial Communications Interface
(SCI)
Block Guide
V02.08
S12SCIV2.pdf
PIM_9C32
Block Diagram
SCI module
SCI
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Asynchronous Serial I/O
The 68HCS12 SCI Interface
Programming the SCI
SCI Interface Using Interrupts
D0
MARK
D1
D2
D3
D4
D5
D6
D7
STOP
SPACE
START
PARITY
ASCII code 54H = 1010100 ("T") sent with odd parity
Common Asynchronous Serial Baud Rates
Baud rate
110
300
600
1200
2400
4800
9600
14400
19200
28800
38400
Bit time
(msec)
9.09
3.33
1.67
0.833
0.417
0.208
0.104
0.069
0.052
0.035
0.026
No. of STOP
bits
2
1
1
1
1
1
1
1
1
1
1
Char. time
(msec.)
100.00
33.3 3
16.67
8.33
4.17
2.08
1.04
0.69
0.52
0.35
0.26
Char./sec.
10
30
60
120
240
480
960
1440
1920
2880
3840
SCI
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Asynchronous Serial I/O
The 68HCS12 SCI Interface
Programming the SCI
SCI Interface Using Interrupts
Name
SC0BDH
SC0BDL
SC0CR1
SC0CR2
SC0SR1
SC0SR2
SC0DRH
SC0DRL
SCI Registers in the MC9S12-C32
Register Addr
Description
00C8
SCI Baud Rate Control Register High
00C9
SCI Baud Rate Control Register Low
00CA
SCI Control Register 1
00CB
SCI Control Register 2
00CC
SCI Status Register 1
00CD
SCI Status Register 2
00CE
SCI Data Register High
00CF
SCI Data Register Low
S CI Control Register 1 (S CxCR1)
S CI Data Re gister H (S CxDRH)
S CI Control Register 2 (S CxCR2)
S CI S tatus Register 1 (SCxSR1)
S CI S tatus Register 2 (SCxSR2)
S CI B aud Ra te Control H (S CxBDH)S CI B aud Ra te Control L (SCxB DL)
T ransmit Sh ift Register
D 8D 7
D6
D5
D4
D3
T ransmit Da ta Register (T DR)
D6
D5
D4
Receive S hift Register
D1
D0
D1
D0
S erial Data Out
P S1 (P S3)
S CxDRL
Receive Data Register (RDR)
D 8D 7
D2
T xD
D3
D2
S erial Data I n
RxD
Functional diagram of the Serial Communications Interface (SCI)
P S0 (P S2)
$00CF
Read:
Write:
7
R7/T7
6
R6/T6
5
R5/T5
4
R4/T4
3
R3/T3
Reads the receive data buffer
Writes to the transmit data buffer
The SCI Data Register Low
2
R2/T2
1
R1/T1
0
R0/T0
SC0DRL
$00CC
7
6
5
4
3
2
1
0
TDRE
TC
RDRF
IDLE
OR
NF
FE
PF
TDRE:
Transmit Data Register Empty Flag
0 – SCxDR busy
1 – Transmit data can be written to SCxDR
TC:
Transmit Complete Flag
0 – Transmitter busy
1 – Transmitter is idle
RDRF:
Receive Data Register Full Flag
0 – SCxDR empty. Cleared by SCxSR1 read with RDRF set, followed by SCxDR read
1 – SCxDR full. Received character can be read from SCxDR
IDLE:
Idle Line Detected Flag
0 – RxD line is idle
1 – RxD line is active
OR:
Overrun Error Flag
0 – No overrun
1 – Overrun detected
NF:
Noise Error Flag
0 – Unanimous decision
1 – Noise on a valid start bit, any data bit, or the stop bit
FE:
Framing Error Flag
0 – Stop bit detected
1 – Zero detected instead of a stop bit
PF:
Parity Error Flag
0 – Correct parity
1 – Incorrect parity
The SCI Status Register 1
SC0SR1
$00CA
7
LOOPS
6
WOMS
5
RSRC
4
M
3
WAKE
2
ILT
LOOPS:
SCI Loop Mode/Single Wire Mode Enable
0 – Normal operation of TxD and RxD
1 – LOOP mode or single wire mode enabled
WOMS:
Wire-Or Mode for Serial Pins
0 – Pins operate in normal mode
1 – Pins declared as outputs operate in open drain fashion
RSRC:
Receiver Source (LOOPS = 1)
0 – Receiver input connected to transmitter internally (not TxD pin)
1 – Receiver input connected to TxD pin (single wire mode)
M:
Mode (Select Character Format)
0 – 8-bit data
1 – 9-bit data
WAKE:
Wakeup by Address Mark/Idle
0 – Wakeup by IDLE line recognition
1 – Wakeup by address mark (most significant data bit set)
ILT:
Idle Line Type
0 – Short idle line mode
1 – Long idle line mode
PE:
Parity Enable
0 – Parity is disabled
1 – Parity is enabled
PT:
Parity Type
0 – Even parity
1 – Odd parity
The SCI Control Register 1
1
PE
0
PT
SC0CR1
$00CE
7
R8
6
T8
5
0
4
0
3
0
2
0
R8:
Receive Data Bit 8
If M bit in SCxCR1 is set, R8 stores the ninth bit of the received data
T8:
Transmit Data Bit 8
If M bit in SCxCR1 is set, T8 stores the ninth bit of the transmitted data
The SCI Data Register High
1
0
0
0
SC0DRH
$00CB
7
TIE
6
TCIE
5
RIE
4
ILIE
3
TE
TIE:
Transmit Interrupt Enable
0 – TDRE interrupts disabled
1 – TDRE interrupts enabled
TCIE:
Transmit Complete Interrupt Enable
0 – TC interrupts disabled
1 – TC interrupts enabled
RIE:
Receiver Interrupt Enable
0 – RDRF interrupts disabled
1 – RDRF and OR interrupts enabled
ILIE:
Idle-Line Interrupt Enable
0 – IDLE interrupts disabled
1 – IDLE interrupts enabled
TE:
Transmitter Enable
0 – Transmitter disabled
1 – Transmitter enabled
RE:
Receiver Enable
0 – Receiver disabled
1 – Receiver enabled
RWU:
Receiver Wakeup Control
0 – Normal SCI Receiver
1 – Wakeup enabled and receiver interrupts inhibited
SBK:
Send Break
0 – Break generator off
1 – Break codes generated as long as SBK = 1
The SCI Control Register 2
2
RE
1
RWU
0
SBK
SC0CR2
$00C8
7
BTST
6
BSPL
5
BRDL
4
SBR12
3
SBR11
2
SBR10
1
SBR9
0
SBR8
SC0BDH
$00C9
7
SBR7
6
SBR6
5
SBR5
4
SBR4
3
SBR3
2
SBR2
1
SBR1
0
SBR0
SC0BDL
SBR[12:0]:
BR divisor; SCI Baud Rate = MCLK / (16 x BR )
The SCI Baud Rate Control Register
Table 11.3 Baud Rate Selection
Desired
BR Divisor for
SCI Baud Rate
MCLK = 8.0 MHz
110
4545
300
1667
600
833
1200
417
2400
208
4800
104
9600
52
14400
35
19200
26
38400
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SCI
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Asynchronous Serial I/O
The 68HCS12 SCI Interface
Programming the SCI
SCI Interface Using Interrupts
sci.asm
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SC0BDH
SC0CR1
SC0CR2
SC0SR1
SC0DRL
RDRF
SCI0
EQU
EQU
EQU
EQU
EQU
EQU
$C8
$CA
$CB
$CC
$CF
$20
;
INITIALIZE SCI
sci0_init
CLR
SC0CR1
LDD
#52
STD
SC0BDH
LDAA
#$0C
STAA
SC0CR2
RTS
;baud rate control
;SCI control reg 1
;SCI control reg 2
;SCI status reg
;SCI data reg
;SCSR mask
;8 bit
;9600 baud
;enable tx & rx
;
INCHAR
INPUT BYTE FROM SERIAL PORT INTO A
LDAA
ANDA
BEQ
LDAA
RTS
;
OUTPUT
SC0SR1
#RDRF
INCHAR
SC0DRL
;check status
;check rdrf
;wait for char
;get char in A
OUTPUT BYTE IN A TO SERIAL PORT
TST
BPL
STAA
RTS
SC0SR1
OUTPUT
SC0DRL
;loop until tdre
;send A
Communicating with a PC
loop:
if key has been pressed
then send character to remote computer
if remote computer has sent character
then display character
repeat loop
Algorithm for a dumb terminal
sciecho.asm
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echo char to PC
org
sci_echo
bsr
se1 bsr
bsr
bra
$4000
sci0_init
inchar
output
se1
#include sci.asm
SCI
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Asynchronous Serial I/O
The 68HCS12 SCI Interface
Programming the SCI
SCI Interface Using Interrupts
;
;
SCI Interface using interrupts File: SCIINT.WHP
display characters from PC keyboard on LCD display
SC0BDH
SC0CR1
SC0CR2
SC0SR1
SC0DRL
RDRF
SCI0.IVEC
EQU
EQU
EQU
EQU
EQU
EQU
EQU
$C8
$CA
$CB
$CC
$CF
$20
$0FD8
ORG
$4000
jsr
jsr
jsr
jsr
jsr
bcs
jsr
ldy
jsr
bra
spi_init
lcd_init
initq
sci0_init
checkq
mn1
data8
#3
ms_delay
mn1
;baud rate control
;SCI control reg 1
;SCI control reg 2
;SCI status reg
;SCI data reg
;SCSR mask
;SCI0 user vector address + 2
main
mn1
;initialize spi
;initialize lcd
;initialize queue
;initialize sci
;if queue is empty
; wait
;store char on LCD
;delay ~10 ms
;
INITIALIZE SCI
sci0_init
SEI
CLR
SC0CR1
LDD
#52
STD
SC0BDH
LDAA
#$2C
STAA
SC0CR2
LDD
#SCI_INTSER
STD
SCI0.IVEC
CLI
RTS
;disable interrupts
;8 bit
;9600 baud
;enable tx & rx, RX INT
;set sci int vector
;enable interrupts
;
Interrupt service routine: get char and store in queue
SCI_INTSER
LDAA
SC0SR1
ANDA
#RDRF
BEQ
SI1
;if RDRF set
LDAA
SC0DRL
;read data (clears RDRF flag)
JSR
QSTORE
;and store it in queue
SI1
RTI
#INCLUDE QUEUE.ASM
#INCLUDE LCD.ASM