Transcript Parallel Interfacing - Computer Science and Engineering at

Parallel Interfacing
Chapter 7
Parallel Interfacing
•
•
•
•
•
•
Parallel I/O Ports
Using Parallel Ports
Seven-Segment Displays
Keypad Interfacing
Liquid Crystal Displays
Interrupt-Driven Traffic Lights
Name
PORTA
PORTB
PORTC
PORTD
PORTE
PORTF
PORTG
PORTH
PORTJ
PORTS
PORTT
PORTAD
Table 7.1 Parallel Ports in the MC68HC812A4
Port Addr
DDR Addr
Alternate Function
0000
0002
High address byte in expanded mode
0001
0003
Low address byte in expanded mode
0004
0006
High data byte in expanded mode
0005
0007
Low data byte in expanded mode
0008
0009
External bus control signals
0030
0032
Chip selects
0031
0033
Memory expansion
0024
0025
Key wakeup
0028
0029
Key wakeup
00D6
00D7
Serial I/O
00AE
00AF
Timer
006F
Input only
A/D converter
Port and Data Direction Registers
Port Data Register
7
Px7
6
Px6
5
Px5
4
Px4
3
Px3
2
Px2
1
Px1
0
Px0
4
DDx4
3
DDx3
2
DDx2
1
DDx1
0
DDx0
PORTx
Port Data Direction Register
7
DDx7
6
DDx6
DDx[7:0]:
5
DDx5
Data Direction for Port x
0 – Input
1 – Output
DDRx
Box 7.1 Parallel I/O Registers - 68HC812A4
\
\
PIOA4.WHP
68HC12 registers for Parallel I/O - MC68HC812A4
HEX
0000
0001
0002
0003
0004
0005
0006
0007
0008
0009
0024
0025
0028
0029
002D
002E
0030
0031
0032
0033
006F
00AE
00AF
00D6
00D7
CONSTANT
CONSTANT
CONSTANT
CONSTANT
CONSTANT
CONSTANT
CONSTANT
CONSTANT
CONSTANT
CONSTANT
CONSTANT
CONSTANT
CONSTANT
CONSTANT
CONSTANT
CONSTANT
CONSTANT
CONSTANT
CONSTANT
CONSTANT
CONSTANT
CONSTANT
CONSTANT
CONSTANT
CONSTANT
PORTA
PORTB
DDRA
DDRB
PORTC
PORTD
DDRC
DDRD
PORTE
DDRE
PORTH
DDRH
PORTJ
DDRJ
PUPSJ
PULEJ
PORTF
PORTG
DDRF
DDRG
PORTAD
PORTT
DDRT
PORTS
DDRS
\
\
\
\
\
\
\
\
\
\
\
\
\
\
\
\
\
\
\
\
\
\
\
\
\
I/O Port A
I/O Port B
Data Direction for Port
Data Direction for Port
I/O Port C
I/O Port D
Data Direction for Port
Data Direction for Port
I/O Port E
Data Direction for Port
I/O Port H
Data Direction for Port
I/O Port J
Data Direction for Port
Port J Pull-up/Pulldown
Port J Pull-up/Pulldown
I/O Port F
I/O Port G
Data Direction for Port
Data Direction for Port
Input Port AD
I/O Port T
Data Direction for Port
I/O Port S
Data Direction for Port
A
B
C
D
E
H
J
Select
Enable
F
G
T
S
Name
PORTA
PORTB
PORTE
PORTP
PORTS
PORTT
PORTDLC
PORTAD
Table 7.2 Parallel Ports in the MC68HC912B32
Port Addr
DDR Addr
Alternate Function
0000
0002
High addr/data byte in expanded mode
0001
0003
Low addr/data byte in expanded mode
0008
0009
External bus control signals
0056
0057
Pulse-width modulator
00D6
00D7
Serial I/O
00AE
00AF
Timer
00FE
00FF
Byte data link communications module
006F
Input only
A/D converter
Box 7.2 Parallel I/O Registers - 68HC912B32
\
\
PIOB32.WHP
68HC12 registers for Parallel I/O - MC68HC912B32
HEX
0000
0001
0002
0003
0008
0009
0056
0057
006F
00AE
00AF
00D6
00D7
00FE
00FF
CONSTANT
CONSTANT
CONSTANT
CONSTANT
CONSTANT
CONSTANT
CONSTANT
CONSTANT
CONSTANT
CONSTANT
CONSTANT
CONSTANT
CONSTANT
CONSTANT
CONSTANT
PORTA
PORTB
DDRA
DDRB
PORTE
DDRE
PORTP
DDRP
PORTAD
PORTT
DDRT
PORTS
DDRS
PORTDLC
DDRDLC
\
\
\
\
\
\
\
\
\
\
\
\
\
\
\
I/O Port A
I/O Port B
Data Direction
Data Direction
I/O Port E
Data Direction
I/O Port P
Data Direction
Input Port AD
I/O Port T
Data Direction
I/O Port S
Data Direction
I/O Port DLC
Data Direction
for Port A
for Port B
for Port E
for Port P
for Port T
for Port S
for Port DLC
MC68HC711E9
Name
PORTA
PORTB
PORTC
PORTCL
PORTD
PORTE
Table 7.3 Parallel Ports in the MC68HC711E9
Port Addr
DDR Addr
Alternate Function
1000
3 in-3 out-2
Timer
i/o
1004
Output only
High address byte in expanded mode
1003
1007
Low addr/data byte in expanded mode
1005
1007
Port C Latched
1008
1009
Serial I/O
100A
Input only
A/D converter
PORTA
Port A Data
$1000
7
PA7
6
PA6
5
PA5
4
PA4
3
PA3
2
PA2
1
PA1
0
PA0
PORTA
5
PAMOD
4
PEDGE
3
DDRA3
2
I4/O5
1
RTR1
0
RTR0
PACTL
Pulse Accumulator Control
$1026
7
DDRA7
6
PAEN
DDRA7:
Data Direction for Bit 7 of Port A
0 – Input
1 – Output
DDRA3:
Data Direction for Bit 3 of Port A
0 – Input
1 – Output
Parallel I/O Control
7
STAF
$1002
6
STAI
5
CWOM
4
HNDS
3
OIN
STAF:
Strobe A Interrupt Status Flag
0 – No edge on STRA
1 – Selected edge on STRA
STAI:
Strobe A Interrupt Enable Mask
0 – STAF does not request interrupt
1 – STAF requests interrupt
CWOM:
Port C Wired-OR Mode
0 – Port C outputs are normal CMOS outputs
1 – Port C outputs are open-drain outputs
HNDS:
Handshake Mode
0 – Simple strobe mode
1 – Full input or output handshake mode
OIN:
Output or Input Handshake Select (HNDS = 1)
0 – Input handshake
1 – Output handshake
PLS:
Pulsed/Interlocked Handshake Operation (HNDS = 1)
0 – Interlocked handshake
1 – Pulsed handshake
EGA:
Active Edge for Strobe A
0 – falling edge
1 – rising edge
INVB:
Invert Strobe B
0 – Active level is logic zero
1 – Active level is logic one
2
PLS
1
EGA
0
INVB
PIOC
Box 7.3 Parallel I/O Registers - 68HC11
\
\
PIO11.WHP
68HC11 registers for Parallel I/O
HEX
1000
1002
1003
1004
1005
1007
1008
1009
100A
CONSTANT
CONSTANT
CONSTANT
CONSTANT
CONSTANT
CONSTANT
CONSTANT
CONSTANT
CONSTANT
PORTA
PIOC
PORTC
PORTB
PORTCL
DDRC
PORTD
DDRD
PORTE
\
\
\
\
\
\
\
\
\
I/O Port A
Parallel I/O Control Register
I/O Port C
Output Port B
Alternate Latched Port C
Data Direction for Port C
I/O Port D
Data Direction for Port D
Input Port E
Parallel Interfacing
•
•
•
•
•
•
Parallel I/O Ports
Using Parallel Ports
Seven-Segment Displays
Keypad Interfacing
Liquid Crystal Displays
Interrupt-Driven Traffic Lights
Turning on an LED
No current
no light
+5V
R
+5V
LED
7406
0
PH5
light
Current
+1. 7V
+5V
R
R=
v oltage
=
current
+0. 2V
LED
5 – 1.7
-3
15 x 10
7406
= 220 ohms
1
PH5
;
;
;
MASK
MSK1
;
;
HI
MASK
8-bit byte
INPUT: B = bit no.
OUTPUT; B = mask = 2^bit#
PSHY
BSR
DB
DB
DB
DB
DB
DB
DB
DB
PULY
ABY
LDAB
PULY
RTS
;save Y
MSK1
1
2
4
8
16
32
64
128
;addr of DB
0,Y
1
;get mask
;restore Y
HI
( b# addr -- )
set bit number b# of byte at address addr to 1
LDY
LDD
BSR
STAB
LDAA
ORAA
STAA
RTS
2,X+
2,X+
MASK
1,-X
0,Y
1,X+
0,Y
;Y = addr
;B = b#
;B = mask
;push B on data stack
;A = @Y
;OR with mask and pop mask
;store back at addr
;
;
LO
LO
( b# addr -- )
clear bit number b# of byte at address addr to 0
LDY
LDD
BSR
COMB
STAB
LDAA
ANDA
STAA
RTS
;
;
;
QHI
QH1
QH2
2,X+
2,X+
MASK
1,-X
0,Y
1,X+
0,Y
;Y = addr
;B = b#
;B = mask
;complement mask
;push B on data stack
;A = @Y
;AND with mask and pop mask
;store back at addr
?HI
( b# addr -- f )
leave a true flag if bit number b# of byte
at address addr is high
LDY
LDD
BSR
STAB
LDAA
ANDA
BEQ
LDD
BRA
LDD
STD
RTS
2,X+
2,X+
MASK
1,-X
0,Y
1,X+
QH1
#$FFFF
QH2
#$0000
2,-X
;Y = addr
;B = b#
;b = mask
;push B on data stack
;A = @Y
;AND with mask and pop mask
;if not zero
; leave true flag
;else leave false flag
;push flag on stack
Using an AC Relay
+5V
AC Voltage
180 Ohms
Relay
+
-
74LS240
Control Signal
AC Voltage Out
Interfacing a switch input
+5V
1K
PH2
HEX
F0 DDRH C!
: ?open
( -- f )
2 PORTH ?HI ;
Parallel Interfacing
•
•
•
•
•
•
Parallel I/O Ports
Using Parallel Ports
Seven-Segment Displays
Keypad Interfacing
Liquid Crystal Displays
Interrupt-Driven Traffic Lights
Common Anode 7-Segment Display
a
+5V
f
b
g
e
c
d
a
b
c
d
e
f
g
Interfacing a 7-Segment Display
d
PH3
14 13
c
PH4
12 11
b
a 1
PH5
10
9
8
14 13
12 11
10
9
f 2
8
1
2
3
4
5
6
7
7406
1
2
3
4
5
6
7
f
NC 4
e
NC
dp
5
6
e 7
PH0
PH1
g
PH2
f
PH6
e
PH7
a
dp
a
3
anode
7406
MAN 72
g
d
14
anode
13
b
b
12
c
11
g
10
c
dp
NC
9 anode
8
d
+5V
220 
anode
HEX
\ File: LED.WHP
FF PORTH C!
CREATE 7seg
7E C,
30 C,
6D C,
79 C,
33 C,
5B C,
5F C,
70 C,
7F C,
7B C,
77 C,
9F C,
4E C,
BD C,
4F C,
47 C,
: .led
\ Port H outputs
\
\
\
\
\
\
\
\
\
\
\
\
\
\
\
\
0
1
2
3
4
5
6
7
8
9
A
b.
C
d.
E
F
( n -- )
7seg + C@
PORTH C! ;
\ get 7seg code
\ store in Port H
Common-Cathode Displays
The MC14495-1
1
2
3
4
5
6
7
8
e
f
g
h+i
A
B
LE
GND
VDD 16
15
d
14
c
13
b
12
a
11
j
10
D
9
C
ANODE-e
ANODE-d
COMMON CATHODE
ANODE-c
ANODE-dp
MC14495-1
1
6
e
2
f
3 d
g
c
4
5
7
a 8
9
b
dp
10
ANODE-g
ANODE-f
COMMON CATHODE
ANODE-a
ANODE-b
MAN 6780
7
6
5
4
3
2
1
0
2 digits: PORTH: 0
0
LE1
LE0
D
C
B
A
HEX
: .digit
( dig# n -- )
30 OR PORTH C!
4 +
DUP PORTH LO
PORTH HI ;
\
\
\
\
keep old
get bit#
bring LE
bring LE
values displayed
for LE
low
high to display digit
Parallel Interfacing
•
•
•
•
•
•
Parallel I/O Ports
Using Parallel Ports
Seven-Segment Displays
Keypad Interfacing
Liquid Crystal Displays
Interrupt-Driven Traffic Lights
4 x 4 Hex Keypad
1
Col
1
2
2
3
3
4
Row
C
4
PJ0
4
5
6
D
3
PJ1
7
8
9
E
2
PJ2
A
0
B
F
1
PJ3
10K
PJ4
PJ5
+5V
PJ6
PJ7
Registers associated with parallel I/O on Port J
Port J Pull-Up/Pulldown Select Register
$002D
7
Bit 7
6
6
5
5
4
4
3
3
2
2
1
1
0
Bit 0
PUPSJ
0
Bit 0
PULEJ
PUPSJ[7:0]: Port J Pull-Up/Pull-Down Select (Initialize before enabling with PULEJ)
0 – Pulldown selected for associated Port J pin
1 – Pull-up selected for associated Port J pin
Port J Pull-Up/Pull-Down Enable Register
$002E
7
Bit 7
6
6
5
5
4
4
3
3
2
2
PUPSJ[7:0]: Port J Pull-Up/Pull-Down Enable
0 – No pull-up/pulldown device for associated Port J pin
1 – Enable pull-up/pulldown device for associated Port J pin
1
1
Scanning a 4 x 4 keypad
load PIOA4.WHP
HEX
: init.key
CREATE keycodes
D7 C,
EE C,
DE C,
BE C,
ED C,
DD C,
BD C,
EB C,
DB C,
BB C,
E7 C,
B7 C,
7E C,
7D C,
7B C,
77 C,
DECIMAL
( -- )
0F DDRJ C!
FO PUPSJ C!
FO PULEJ C! ;
\
\
\
\
\
\
\
\
\
\
\
\
\
\
\
\
\
key
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
\
\
\
\
PJ0-PJ3 outputs
PJ4-PJ7 inputs
PJ4-PJ7 pullups
enable pullups
row
1
4
4
4
3
3
3
2
2
2
1
1
4
3
2
1
col
2
1
2
3
1
2
3
1
2
3
1
3
4
4
4
4
Scanning a 4 x 4 keypad
: ?keypad
: keypad
( -- ff | n tf )
0 keycodes
16 0 DO
DUP I + C@
DUP PORTJ C!
PORTJ C@ =
IF
DROP I TRUE
ROT LEAVE
THEN
LOOP
DROP ;
( -- n )
BEGIN
?keypad
UNTIL ;
\
\
\
\
\
\
\
\
ff pfa
ff pfa
ff pfa code
ff pfa code
ff pfa flag
ff pfa
ff n tf
n tf ff
\ ff pfa
Axiom Keypad
\
Hex keypad decoding
\
Axiom keypad -- CME12A4
HEX
24 CONSTANT PORTH
25 CONSTANT DDRH
DECIMAL
: 10msec.delay
( -- )
864 FOR NEXT ;
HEX
: init.key
( -- )
0F DDRH C! ;
\ PH0-PH3 outputs
\ PH4-PH7 inputs
Axiom 4 x 4 Hex Keypad
1
Col
1K
1
2
2
3
3
4
Row
A
4
PH0
4
5
6
B
3
PH1
7
8
9
C
2
PH2
*
0
#
D
1
PH3
PH4
PH5
PH6
PH7
CREATE keycodes
D7 C,
EE C,
DE C,
BE C,
ED C,
DD C,
BD C,
EB C,
DB C,
BB C,
7E C,
7D C,
7B C,
77 C,
E7 C,
B7 C,
\
\
\
\
\
\
\
\
\
\
\
\
\
\
\
\
\
key
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E/*
F/#
row
1
4
4
4
3
3
3
2
2
2
4
3
2
1
1
1
col
2
1
2
3
1
2
3
1
2
3
4
4
4
4
1
3
DECIMAL
: ?keypad
: keypad
( -- ff | n tf )
0 keycodes
16 0 DO
DUP I + C@
DUP PORTH C!
PORTH C@ =
IF
DROP I TRUE
ROT LEAVE
THEN
LOOP
DROP ;
( -- n )
BEGIN
?keypad
UNTIL ;
\
\
\
\
\
\
\
\
ff pfa
ff pfa
ff pfa code
ff pfa code
ff pfa flag
ff pfa
ff n tf
n tf ff
\ ff pfa
Debounce
: getkey
( -- n )
BEGIN
keypad
10msec.delay
keypad
OVER <>
WHILE
DROP
REPEAT ;
\
\
\
\
n1
debounce
n1 n2
n1 f
: wait.for.keyup
( -- )
BEGIN
BEGIN
?keypad
WHILE
DROP
REPEAT
10msec.delay
?keypad
WHILE
DROP
REPEAT ;
\ debounce
: main.keypad
( -- )
init.key
BEGIN
getkey
CR .
wait.for.keyup
AGAIN ;
Displaying keys pressed on a 7-segment display
: keypad
( -- n )
BEGIN
?keypad
UNTIL ;
: wait.for.keyup
: main.keypad
( -- )
BEGIN
?keypad
WHILE
DROP
REPEAT ;
( -- )
init.key
BEGIN
keypad
.led
wait.for.keyup
AGAIN ;
Including debounce when reading a keypad
DECIMAL
: getkey
( -- n )
BEGIN
keypad
10MS.DELAY
keypad
OVER <>
WHILE
DROP
REPEAT ;
: wait.for.keyup
\
\
\
\
n1
debounce
n1 n2
n1 f
( -- )
BEGIN
BEGIN
?keypad
WHILE
DROP
REPEAT
10MS.DELAY
?keypad
WHILE
DROP
REPEAT ;
\ debounce
The 74C922 16-Key Encoder
1
X1 X2 X3 X4 Y4 Y3 Y2 Y1
2
NC
3
3
2
1
0
4
1
2
3
C
5
7
6
5
4
4
5
6
D
B
A
9
8
7
8
9
E
F
E
D
C
A
0
B
F
0.1 f
6
1.0 f
7
8
9
ROW Y1
Vcc
ROW Y2
DATA OUT A
ROW Y3
DATA OUT B
ROW Y4
DATA OUT C
OSC
DATA OUT D
KB MASK
COL X4
OUT EN
DATA AV
COL X3
COL X1
GND
COL X2
MM74C922
18
17
16
15
14
PJ0
PJ1
PJ2
PJ3
13
12
11
10
PJ7
Reading a keypad using
the 74C922 16-Key Encoder
HEX
CREATE keytbl
C C, 3 C, 2 C, 1 C, D C, 6 C, 5 C, 4 C,
E C, 9 C, 8 C, 7 C, F C, B C, 0 C, A C,
: init.key
: getkey2
( -- )
00 DDRJ C! ;
\ Port J inputs
\ Read hex value from keypad
( -- n )
BEGIN
7 PORTJ ?HI
UNTIL
PORTJ C@
0F AND
keytbl + C@ ;
Interfacing a 16 x 1 hex keypad to a
68HC711E9 using a 74154
+5V
10K
STRB
PB0
23
PB1
22
PB2
21
PB3
20
18
19
0
1
74154
2
3
4
5
A
6
7
B
8
9
C
10
11
D
12
13
14
15
1
2
3
4
5
6
7
8
9
10
11
13
14
15
16
17
STRA
Scanning a 16 x 1 keypad
DECIMAL
: init.key
( -- )
0 PIOC C! ;
\ pulse STRB lo, falling edge of
STRA
: ?keypad
( -- ff | n tf )
0
16 0 DO
I PORTB C!
7 PIOC ?HI
IF
PORTCL C@ DROP
DROP I TRUE
LEAVE
THEN
LOOP ;
\
\
\
\
\
\
\
\
\
ff
ff
ff
pulses STRB low
ff flag
ff
clear STAF
n tf
n tf
ff
Parallel Interfacing
•
•
•
•
•
•
Parallel I/O Ports
Using Parallel Ports
Seven-Segment Displays
Keypad Interfacing
Liquid Crystal Displays
Interrupt-Driven Traffic Lights
Liquid Crystal Display
VDD
20K
PH0 ( DB0)
PH1 ( DB1)
PH2 ( DB2)
PH3 ( DB3)
PH4 ( DB4)
PH5 ( DB5)
PH6 ( DB6)
PH7 ( DB7)
PJ2 (E)
PJ1 (R/W)
PJ0 (RS)
Vo
1 2 3
4 5 6 7 8 9 10 11 12 13 14
16 x 1 Li quid Crys tal Di splay
Relationship between RS, R/W, and E
RS
R/W
E
Operat ion
0
0
Write instruct ion code
0
1
Read busy f lag and address counter
1
0
Write data
1
1
Read data
Table 7.4 HD44780 Instruction Set
Instruction
Clear display
Return home
Entry mode set
Display ON/OFF
control
Cursor or display
shift
Function set
Set the CG RAM
address
Set the DD RAM
address
Read busy flag &
address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Description
0
0
0
0
0
0
0
1 Clears display & returns cursor to home.
Sets I/D=1 in Entry Mode.
0
0
0
0
0
0
1
x Returns cursor to home position (Address 0)
Set DD RAM address to zero.
0
0
0
0
0
1
I/D S I/D=1: increment cursor; S=0: normal ;
I/D=0: decrement cursor; S=1 shift display.
0
0
0
0
1
D
C
B Sets ON/OFF all display (D), cursor (C),
and blink of cursor (B).
0
0
0
1 S/C R/L x
x S/C=1: display shift; S/C=0: cursor move;
R/L=1: shift right; R/L=0: shift left.
0
0
1 DL N
F
x
x DL=1: 8 bits; DL=0: 4 bits; N=1: 2 line;
N=0: 1 line; F=1: 5x10 dots; F=0; 5x7 dots.
0
1
CG RAM address
Sets the CG RAM address, after which
CG RAM data is sent and received.
1
DD RAM address
Sets the DD RAM address, after which
DD RAM data is sent and received.
BF
Address counter
Read busy flag (BF) and address counter
contents.
Listing 7.1 LCD
\
\
\
Liquid Crystal Display
Data byte: PORTH
Control: PORTJ
RS: PJ0
R/W: PJ1
E: PJ2
LOAD HEX2ASC.WHP
HEX
: RS
( -- )
0 PORTJ;
\ L: instr;
H: data
: R/W
( -- )
1 PORTJ;
\ H: read;
: E.
( -- )
2 PORTJ;
\ Enable signal: H->L
: .1ms.delay
( -- )
67 FOR NEXT ;
: 4.1ms.delay
( -- )
2976 FOR NEXT ;
: lcd.setup
( -- )
FF DDRH C!
07 DDRJ C!
R/W LO
RS LO
E. LO ;
L: write
\ Port H outputs
\ PJ0–P2 outputs
\ Used during LCD initialization when busy flag cannot be checked
: >inst
( n -- )
\ write lcd instruction
.1ms.delay
\ wait for busy = 0
PORTH C!
R/W LO
RS LO
E. HI E. LO ;
: busy.wait
( -- )
\ wait for busy flag
00 DDRH C!
\ make Port H
R/W HI
RS LO
BEGIN
E. LO E. HI
PORTH C@
\ read port H
E. LO
80 AND NOT
\ until
UNTIL
R/W LO
FF DDRH C! ;
\ make Port H
to go to zero
inputs
bit 7 is zero
outputs
: >instr
( n -- )
busy.wait
PORTH C!
R/W LO
RS LO
E. HI E. LO ;
\ write lcd instruction
\ wait for busy = 0
: >data
( n -- )
busy.wait
PORTH C!
R/W LO
RS HI
E. HI E. LO ;
\ write lcd data
\ wait for busy = 0
: init.lcd
( -- )
30 >inst
4.1ms.delay
30 >inst
.1ms.delay
30 >inst
30 >inst
8 >inst
1 >inst
6 >inst
F >inst
80 >inst ;
\ set function, 8 bit, 1 line
\ set function, 8 bit, 1 line
\
\
\
\
\
\
\
: clear.lcd
( -- )
1 >instr
4.1ms.delay ;
: hex>lcd
( hex -- )
HEX2ASC >data ;
set function, 8 bit, 1 line
set function, 8 bit, 1 line
display off, cursor on, blink
clear display
entry mode set, inc cursor
display on, cursor on, blink
set DD RAM addr to 0000000
Axiom LCD
\
LCD for Axiom CME-12A4
load hex2asc.whp
load string.whp
HEX
3F0
CONSTANT lcdinstr
3F1
CONSTANT lcddata
DECIMAL
: 4.1ms.delay
( -- )
2982 FOR NEXT ;
HEX
\
Write instruction
: >instr
( n -- )
lcdinstr C! ;
\
Write data
: >data
( c -- )
lcddata C! ;
: lcd.init
( -- )
3C >instr
4.1ms.delay
1 >instr
4.1ms.delay
0f >instr
4.1ms.delay
6 >instr
14 >instr
2 >instr
4.1ms.delay
0A BASE ! ;
\ 2 x 40 display
\ clear & home
\ display on
\ cursor shift off
\ shift display left
\ cursor to home
\ decimal default
Table 7.4 HD44780 Instruction Set
Instruction
Clear display
Return home
Entry mode set
Display ON/OFF
control
Cursor or display
shift
Function set
Set the CG RAM
address
Set the DD RAM
address
Read busy flag &
address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Description
0
0
0
0
0
0
0
1 Clears display & returns cursor to home.
Sets I/D=1 in Entry Mode.
0
0
0
0
0
0
1
x Returns cursor to home position (Address 0)
Set DD RAM address to zero.
0
0
0
0
0
1
I/D S I/D=1: increment cursor; S=0: normal ;
I/D=0: decrement cursor; S=1 shift display.
0
0
0
0
1
D
C
B Sets ON/OFF all display (D), cursor (C),
and blink of cursor (B).
0
0
0
1 S/C R/L x
x S/C=1: display shift; S/C=0: cursor move;
R/L=1: shift right; R/L=0: shift left.
0
0
1 DL N
F
x
x DL=1: 8 bits; DL=0: 4 bits; N=1: 2 line;
N=0: 1 line; F=1: 5x10 dots; F=0; 5x7 dots.
0
1
CG RAM address
Sets the CG RAM address, after which
CG RAM data is sent and received.
1
DD RAM address
Sets the DD RAM address, after which
DD RAM data is sent and received.
BF
Address counter
Read busy flag (BF) and address counter
contents.
: clear.lcd
( -- )
1 >instr
4.1ms.delay ;
: hex>lcd
( hex -- )
HEX2ASC >data ;
: type.lcd
( addr len -- )
?DUP
IF
0 DO
DUP C@
>data 4.1ms.delay 1+
LOOP
THEN
DROP ;
: .lcd
( n -- )
(.) type.lcd ;
: u.lcd
( u -- )
(u.) type.lcd ;
DECIMAL
Parallel Interfacing
•
•
•
•
•
•
Parallel I/O Ports
Using Parallel Ports
Seven-Segment Displays
Keypad Interfacing
Liquid Crystal Displays
Interrupt-Driven Traffic Lights
State
1
2
3
4
5
6
Red
Red
Y ellow
Y ellow
Green
Green
North - South
East - West
Table 7.5 Traffic Light States
North - South
East - West
Green
Red
Yellow
Red
Red
Red
Red
Green
Red
Yellow
Red
Red
Delay (sec.)
5
1
1
5
1
1
Listing 7.2 Traffic Lights Using Real-time Interrupt
\
\
HEX
0014
0015
0024
0025
0B30
TABLE DRIVEN TRAFFIC LIGHTS
using RTI interrupts
CONSTANT
CONSTANT
CONSTANT
CONSTANT
CONSTANT
File: TRAFFIC.WHP
RTICTL
RTIFLG
PORTH
DDRH
RTI.IVEC
VARIABLE DTIME
CREATE LIGHTS
\
Lights table
6
C,
2
C,
18
C,
5 3D * C,
28
C,
3D
C,
48
C,
3D
C,
42
C,
5 3D * C,
44
C,
3D
C,
48
C,
3D
C,
\
\
\
\
\
\
\
\
\
\
\
\
\
\
_RYGRYG_ = Port H
number of states
pointer to next state
00011000
5 sec. delay - $3D = 61 ticks per second
00101000
1 sec. delay
01001000
1 sec. delay
01000010
5 sec. delay
01000100
1 sec. delay
01001000
1 sec. delay
Traffic Lights Using Real-time Interrupt
: RTIF.CLR
( -- )
80 RTIFLG C! ;
: RTI.SET16
( -- )
05 RTICTL C! ;
: RTI.INT.ENABLE
( -- )
7 RTICTL HI ;
: RTI.INT.DISABLE
( -- )
7 RTICTL LO ;
\ clear RT1 flag
\ set RTI rate to 16.384 msec
Traffic Lights Using Real-time Interrupt
INT: RTI.INTSER
( -- )
DTIME @ 1DUP 0=
IF
DROP LIGHTS DUP 1+ C@
DUP 2 PICK C@
2* 1+
>
IF
DROP 2
THEN
2DUP + DUP C@ PORTH C!
1+ C@
ROT 1+
ROT 2+ SWAP C!
THEN
DTIME !
RTIF.CLR
RTI;
: SET.RTI.INTVEC
( -- )
[ ' RTI.INTSER ] LITERAL
RTI.IVEC ! ;
\ ticks
\
\
\
\
ticks
pfa ptr
pfa ptr ptr cnt
pfa ptr ptr ptrmax
\
\
\
\
\
\
\
pfa ptr
cycle back
pfa ptr
pfa ptr addr
pfa ptr ticks
ptr ticks pfa+1
update ptr
Traffic Lights Using Real-time Interrupt
: INIT.TRAFFIC
: MAIN.TRAFFIC
( -- )
FF DDRH C!
RTI.SET16
SET.RTI.INTVEC
RTI.INT.ENABLE
1 DTIME ! ;
\
\
\
\
\
Port H outputs
set RTI rate to 16.384 ms
set interrupt vector
enable RTI interrupts
start on 1st interrupt
( -- )
SEI
INIT.TRAFFIC
CLI ;
: TURNOFF
SEI
0 PORTH C!
RTI.INT.DISABLE ;
DECIMAL
\ turn off leds
Box 7.4 WHYP Port Bit Set and Test Words
HI
( b# addr -- )
Set bit number b# of the byte at address addr to 1.
LO
( b# addr -- )
Clear bit number b# of the byte at address addr to 0.
?HI
( b# addr -- f )
Leave a true flag on the data stack if bit number b# of the byte at address addr is high.