Transcript PLD Basics - Docweb Thomas More Kempen

PLD Technology Basics
Basic PAL Architecture
Fuse
CLK
D
OE
Q
Q
Technology
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The type of the configuration cell (Memory) defines the technology
Bipolar
– metallic fuse, destroyed by prog., One-Time-Programmable (OTP)
UV erasable (EPROM)
– expensive window package or Plastic OTP, slow erase time
Electrical erasable (EEPROM)
– multiple read/write cycles, In-System programmable,
fast prog and erase, non-volatile
CMOS-Memory Cell
– volatile, information lost after power-down, reconfigurable, very fast
prog. Time, Configuration PROM needed
Antifuse, Vialink
– open fuse element, programming forms an electrical connection,
OTP, long prog times, low impedance interconnect
PAL Architecture
Clock/Input
OR Gates
Programmable AND Array
Dedicated
Inputs
SPLDs use a programmable AND array and
fixed OR array to create several outputs in a
sum-of-products form. SPLDs are commonly
referred to as PALs.
PAL
Output
Macrocells
I/Os
From OR Gate
These outputs can be either
combinatorial or registered in the
macrocell.
D Q
Clock
To AND Array
Q
I/O
CPLD Architecture (1)
I/Os
PAL Block
I/Os
PAL Block
Central Switch Matrix
Dedicated
inputs
PAL Block
I/Os
PAL Block
I/Os
Clock/
Inputs
The CPLD is an array of PAL-like devices, interconnected by a switch matrix.
CPLD Architecture (2)
Logic Array
& Allocator
Central Switch Matrix
Output
Macrocell
Output Switch
Matrix
Clock Generator
Clock/Input
I/O
Cells
I/O
The CPLD architecture is more
complex than the typical PAL in
order to fully utilize the increased
logic capacity and additional
routing matrices of the device.
Input Switch Matrix
From Logic
Allocator
D
Q
To Output/Input
Switch Matrix
From
Clock
Generator
The CPLDmacrocell, although relatively similar to the
PAL macrocell, has greater flexibility in routing its
output to both the I/O Cells and Central Switch Matrix.
Product Term Enable
From Output Switch
Matrix
To Input Switch
Matrix
I/O
Q D
From Clock
Generator
The I/O Cell controls the flow of input
and output to and from the device.
MACH 4A Device Architecture
PAL Block
Clock/
Input Pins
Dedicated
Input Pins
Central Switch Matrix
Clock
Generator
Logic Array
and
Allocator
Output/
Buried
Macrocells
Output
Switch
Matrix
I/O Cells
I/O Pins
Input
Switch
Matrix
Macrocell Feedback
I/O Pin Feedback (registered and non-registered)
I/O Pins
PAL Block
PAL Block
FPGA Architecture
Configurable Logic
Block (CLB)
Programmable
Interconnect
I/O Block
Routing
FPGAs utilize a channeled routing structure
to connect blocks of configurable logic
FPGA
Applications
Variable Grain Architecture
Datapath Functions
Register
Intensive
Functions
• Register Intensive
• Narrow Gating
• Pipelined Systems
• Dense, Flexible
• Low Power
• Lower Speed
than CPLDs
Control Functions
• High Speed
• Wide Gating
• State Machines
• Address Decoding
CPLD
Combinatorial Functions
Measurement of Size and Density
• SPLD
– Measured by number of input/outputs (22V10)
• ASIC
– Available gates measured in 2-input equivalents
– Usable gates typically 40 to 60 %
• CPLD
– Measured by macrocells (32 -1024)
– Typical gate count ranges 1k to 40k
• FPGA
Attention!
The Art of Gate Counting
– Measured by gate count (1k to 100k)
– Usable gates typically 50 to 60 %
In-System Programming Eases
Prototyping
• Easy development
• Connect cable to PC, programmer or JTAG tester
• Download software performs the following:
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Bulk Erases the device (EE only)
Serializes the JEDEC (fusemap) file
“Bypasses” devices not being programmed
Shifts the JEDEC data into the device
Programs the JEDEC data into the configuration cells
JTAG-Testing
Core
Logic
Core
Logic
TDO
TDI
TMS
TCK
Boundary Scan
Control Circuit
TDI
TMS
TCK
TDO
Boundary Scan
Control Circuit
TMS
TCK
TDO
JTAG-Interface
Boundary-Scan Cell (BSC)