Transcript PAL/PLA struktuur

Testing of PLA and PAL.
PAL/PLA structure
x1 x2
xn
...
Buffer
.
.
.
AND
OR
...
y1 y2
x1
x2
1
ym
0
xn
1
...
...
1
+V
.
.
.
+V
y1
y2
ym
Example.
y1 = x1 x2 x3 + x1 x2 x3 + x1 x2
y2 = x1 x2 x3 + x1 x2
x1
x2
1
0
x3
1
1
+V
y1
y2
Models of fault in PLA-s and PAL-s
1.
2.
3.
Permanent constant faults;
Short-circuits;
Crosspoint Faults ;
appearance of CP-s in the
AND array;;
disappearance of CP-s from
the AND array;
appearence of CP-s in the
OR array;
disappearance of CP-s from
the OR array.
Classical model of fault: constant 1 and 0 (Stuck-at-0, Stuck-at-1, s-a-0, s-a-1)
s-a-0
X
s-a-1
f
X
f
Short
X
f1
X
f1
X
X
f2
Permanent constant faults in PLA/PAL-s
y1 = x1 x2 x3 + x1 x2 x3 + x1 x2
X3 s-a-1fault
y2 = x1 x2 x3 + x1 x2
x1
x2
1
y1 = x1 x2 + x1 x2 x3 + x1 x2
y2 = x1 x2 + x1 x2
0
x3
1
1
+V
s-a-1
y1
y2
Crosspoint Faults
Appearance of CP-s to in the AND array
Unnecessary
variable
Shrinkage fault
y1 = x1 x2 x3 + x1 x2 x3 + x1 x2
y1 = x1 x2 x3 + x1 x2 x3 + x1 x2 x3
Unnecessary CP
y2 = x1 x2 x3 + x1 x2
x1
x2
1
y2 = x1 x2 x3 + x1 x2 x3
0
x3
1
1
+V
Carnaugh Map
Faultless
y2
x1
0
Faulty
y2
x2x3
00
01
1
0
y2
y1
x2x3
11 10
0
0
0
00
01
11 10
1
0
0
0
0
0
1
0
x1
1
0
0
1
1
1
Disappearance of CP-s from the AND array
Growth fault
y1 = x1 x2 x3 + x1 x2 x3 + x1 x2
y1 = x1 x2 x3 + x1 x2 x3 + x1 x2
CP does not exist
y2 = x1 x2 x3 + x1 x2
y2 = x1 x2 x3 + x1
CP does not exist x 1
x2
1
0
x3
1
1
+V
Carnaugh Map
Faultless
y2
x1
0
Faulty
y2
x2x3
00
01
1
0
y2
y1
x2x3
11 10
0
0
0
00
01
11 10
1
0
0
0
1
1
1
1
x1
1
0
0
1
1
1
Appearance of a new CP to the OR-array
Appearance fault
y1 = x1 x2 x3 + x1 x2 x3 + x1 x2
y1 = x1 x2 x3 + x1 x2 x3 + x1 x2
Unnecessary CP
y2 = x1 x2 x3 + x1 x2
x1
x2
1
y2 = x1 x2 x3 + x1 x2 + x1 x2 x3
0
x3
1
1
+V
Carnaugh Map
Faultless
y2
x1
0
Faulty
y2
x2x3
00
01
1
0
y2
y1
x2x3
11 10
0
0
0
00
01
11 10
1
0
0
0
0
1
1
1
x1
1
0
0
1
1
1
Disapperance of the CP from the OR-array
Disappearance fault
y1 = x1 x2 x3 + x1 x2 x3 + x1 x2
y2 = x1 x2 x3 + x1 x2
y1 = x1 x2 x3 + x1 x2 x3 + x1 x2
CP does not exist
y2 = x1 x2 x3
x1
x2
1
0
x3
1
CP
does not
exist
1
+V
y1
Carnaugh Map
Faultless
y2
x1
0
Faulty
y2
x2x3
00
01
1
0
x2x3
11 10
0
0
y2
0
00
01
11 10
1
0
0
0
0
0
0
0
x1
1
0
0
1
1
1
Missing CP-s are equivalent to some constant faults (Stuck-at-0/1)
but additional CP-s do not
corrspond to that model.
n – number of inputs
m – number of terms
k – number of outputs
(2n + k) – different single and manifold CP faults
(2n + k)m
2
- 1 -different single and manifold CP faults
CP faults may be untestifyiable in case of excessive functions
For example:
The missing of CP corresponding to whichever variable
is not testifyiable in the AND array.
y1 = x1 + x2 + x1 x2 = x1 + x2
The missing of CP corresponding to this term is not
testifyiable in the
OR array.
Generation of tests for PLA-s and PAL-s
1.
2.
3.
4.
5.
Traditional methods for circuits equivalent to PAL/PLA-s;
Random testing
Exhaustive testing
Semirandom methods
Deterministic Methods
Traditional methods for equivalent circuits.
&
1
&
Cons:
1.Ineffective due to convergent branching
2. CP faults cannot be described as traditional s-a-0/1 faults.
Random testing
.
.
.
Random
combinations
Reactions
PAL/PLA
Discovery of the fault in AND array.
s-a-0
0011
X
&
00 0 0
0110
Bringing the impact of the
fault to the output
through OR array
0/1 0 1 1/0
0
1
0/1 1 1 1/0
11 0
s-a-1
0011
X
&
0 1 10
0110
Cons:
1.
A very large number of tests as in AND array combinations
where only one input is 1 and the rest are 0s
can be used as tests.
2.
A very large number of tests as the transport through the OR
array requires that one input equals 1 and
the rest are 0s.
Exhaustive testing and semirandom methods
Exhaustive testing
All possible
combinations
.
.
.
PAL/PLA
Reactions
Cons: A large number of tests when real arrays are considered
(for example, 50 inputs, 67 outputs,
190 terms)
Semirandom method
Generator of
pseudorandom
numbers
.
.
.
Random numbers are not used.
In stead, numbers with only
one 0 are used.
Reactions
PAL/PLA
0 1 1
1 0 1
1 1 0
&
Deterministic Test Generation
Special algorithms oriented at the structure of the array and testing of CP-s.
Example: let us test whether x1x2 has been
Added in the function y2 with CP x3.
x1
x2
1
1
1
y1 = x1 x2 x3 + x1 x2 x3 + x1 x2
y2 = x1 x2 x3 + x1 x2
0
x3
0
1
1
+V
0
0
1
1/0
0
y1
Let us define the operation: a # b = a b
y2
1/0
Activating the impact of the fault: a = term that can be tested without faults
b = term than can be tested with faults
Example. x1 x2 # x1 x2 x3 = x1 x2(x1 x2 x3) = x1 x2 x3
Transport of the impact of the fault to the output: a =result of
the previous operation, b =functiwithout the tested term
Example. x1 x2 x3 # x1 x2 x3 = x1 x2 x3 (x1 x2 x3 ) = x1 x2 x3
Test :
x1 = 1
x2 = 1
x3 = 0
Testable PLA Design
What is the objective?
Concurrent testing
Yes
No
Self-testing
Fault masking
Yes
Yes
No
No
Test generation
Yes
No
Yes
Special Design
No
Must be taken into consideration:
1.
Indicators of testability;
2. Impact on the original design;
3.
Requirements for the testing environment;
4.
Cost of design
Examples of testable PLA/PAL-s
Concurrent testing of PAL/PLA-s I
x1 x2
xn
...
.
.
.
AND
OR
Additional
line
Buffer
TSC
1-out-of-m
code checker
f
TSC
Two-rail Checker
f
g
y1 y2 . . . y m Parity check
g
faultless/faulty
Totaly Self Cheking (TSC) Two-rail Checker
x 0 x1
y0 y1
TSC
Two-rail Checker
f
g
If x0 = y0 and x1 = y1 then f = g
x0 x1
y0 y1
f
g
0
1
0
1
0
1
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
Concurrent testing of PAL/PLA-s I
(using the Berger code)
x1 x2
xn
y1 y2 . . .
ym
...
AND
.
.
.
OR
Additional
lines
Buffer
Control code
generator
TSC
Two-rail Checker
f
g
Inverse value of the Control code
control code
Berger code
Orders of info Order of control (number of 0s in the code)
01101011
011
Control order
generator
Orders of info
Comparison
scheme
True/false
Orders of control
Modifyied Berger code for a set of functions.
x 3x4
y1
x1 x 2
00
01
00
0
1
1
0
01
0
0
1
1
11 10
x1 x2
00
01
11 10
00
1
0
0
1
01
0
0
1
1
11
1
0
1
0
11
1
0
0
0
10
0
0
1
1
10
0
0
1
1
x3x4
y3
x 1 x2
x3x4
y2
x3x4
c1 c2
00
01
11 10
00
01
11 10
00
1
0
0
0
00
01
10
10
10
01
0
1
0
1
01
11
10
01
00
11
1
0
0
1
11
00
11
10
10
10
0
1
1
1
10
11
10
00
00
x 1 x2
PAL/PLA testable with universal tests
It is possible to test an array without knowing how it
has been programmed. The testing is not concurrent.
Decoder of the modified inputs
x1
xn
...
z2
Parity check
.
.
.
AND
Parity check
s1
...
Selection of terms
c1
c2
OR
sm
sm+1
Additional line
...
y1 y2
yk
Decoder of the modified
inputs
c1 c2
&
b2i-1
xi
1
&
b2i
z1
Additional
line
Universal tests
I1
Ij0
Ij1
Ji0
Ji1
x1 … xi … xn
- … - … For j=1, … , m
0 … 000 … 0
1 … 111 … 1
For I=1, … , n
1 … 101 … 1
0 … 010 … 0
em =
c1 c2
- -
s1 … sj … sm
0 … 0 … 0
z1 z2
0 0
1 0
0 1
0 … 010 … 0
0 … 010 … 0
1 1
1 1
0 1
1 0
1 … 111 … 1
1 … 111 … 1
em em -
0, if m is odd
1, if m is even
The length of the tests is 1+m+n, where
m is the number of terms and n is that of inputs.
A built-in Self-Testable PLA with Cumulative Parity
Comparision
T
xor
D
Decoder of the modified inputs
x1
z
xn
...
s1
AND
(the number of
used CP-s at each line
must be odd))
.
.
.
OR
(the number of
used CP-s
mt each line must
be even)
sm
sm+1
Additional line
...
y1 y2
yk
While transmitting universal tests (n+m+1) the trigger takes at
each test series the
opposite value according to the previous series.
Additional
line
Parity check
...
Selection of terms
c1
c2
Methods using signature
LFSR - Linear Feedback Shift Register
T
T
T
+
T
+
Signature Analyzer
Parallel.
Signals from the checked object
T
+
+
T
T
+
+
T
Series
+
T
+
Signal from
the checked
object
T
T
T
LFSR
(Generator of
pseudorandom
numbers)
x1 x2
All possible input combinations
may be used
instead of the generator of
pseudorandom
numbers
xn
...
Buffer
AND
Signature
analyzer I
.
.
.
OR
y1 y2
...
ym
Signature
analyzer II
PLA/PAL with BILBO-s.
BILBO – Built-in Logic-Block Observer
LFSR that can be activated as the generator of pseudorandom numbers
or as signature analyzer (depending on the conditions chosen)
x1 x2 . . .
xn
Buffer
BILBO I
BILBO II
AND
.
.
.
OR
BILBO III
y1 y2 . . . y m
More methods for improving the testability
1.
Counting of CP-s. Presupposes the conductivity of bit lines and term
lines.
Presupposes that the expected CP numbers are known (functioning array)
2. feedback from the signature analyzer to the inputs
(to the LFSR generating pseudorandom values). Thus ate these blocks united
into one.
3. several signature analyzers are used for testing both the AND and OR
part.
For example, one is used for testing even bit lines and the other for odd. It
results
in the better use of the chip area as the analyzer behind the bit lines requires
more
space than the bit lines.
4. AND and OR arrays are divided into parts that enables to test them
simultaneously. Presupposes that additional requirements are set for thr
programming of PAL/PLA-s.