PowerPoint 簡報 - National Sun Yat
Transcript PowerPoint 簡報 - National Sun Yat
With a significant increase in the design complexity of cores
and associated communication among them, post-silicon
validation has become a demanding task in System on Chips
(SoCs) design. To ensure that final products are fault-free and
ready for market, the post-silicon validation goal is to catch
bugs and pinpoint the root causes of errors that could escape
from pre-silicon verification tools. Post-silicon validation
involves running a hardware prototype in an environment that is
similar to its final platform with its expected workload.
As new SoCs tend to have many cores, the interactions among
these cores are becoming so complex that post-silicon debug
techniques should address not only validation of the functional
aspects of a design but such techniques have to “bulletproof”
the communication and synchronization among cores inside an
In this paper, we propose an AXI based environment for postsilicon validation. The proposed environment involves Local
Debugging Unit (LDU) and Shared Debugging Unit (SDU).
LDU monitors trace of transactions issued by the hardware
prototype and detect undesired conditions on bus. SDU
combines debug traces from different LDUs. We embed the
proposed SDU inside an AXI configurable interconnect. Major
benefits of using our proposed debug platform over traditional
techniques for silicon validation are as follows: 1) it detects and
bypasses real time severe faulty conditions such as deadlocks
resulting from design errors or electrical faults 2) there is no
need for internal trace memory because SDU can communicate
to the external memory through slave ports 3) it enables online
monitoring of the trace buffer.
Achieve the required
mechanism in AXIbased system
Assertion checker in
inside the bus
Design errors and the electrical errors are two major source of failure in first-silicon.
Conventional debug methods and tools tend to focus more on the computational part of a
system. e. g. the processor and its interaction with main memory.
LDU: They are distributed among AXI Master Interfaces that connect master devices to the
bus. They trace the transaction signals and detect the undesired condition.
SDU: LDUs are connected to the central SDU and transmit their debug traces to that module.
And then schedule it to external memory. It is implemented inside AXI interconnection.
Design error and electrical error may lead to following error.
len: number of transfer
If slave expected more data transfer but master is waiting ack from slave.
If slave expected less data transfer but master still transfer.
It usually happens when multiple master are writing to the same place.
The result is different depend on the order.
a system performs continuously the same sequence of operations without any
changes in the status of that system.
It occurs because data dependency.
Master issue a tansfer
If the corresponding TR has already set.
If set, add new line in transaction table(valid, transaction ID, number of
request, expected transaction ID). If it doesn’t set, set 1 and add new line.
Slave response: Compare the expected ID at transaction table to detect if it
violates the order.
Assertion checker has 83 statement. They use MBAC for converting them to
SDU combines trace information from LDUs and schedules them to the trace
memory. SDU traces failure patterns that might lead to erroneous conditions
The platform include 2 16-bit SAYEH processors.
They intentionally inserted design error in the processors, memory controller,
The errors are tuned to represent the corner case.
Memory controller: memory scheduler
Processor: inject fault into forwarding unit, cache controller and interrupt controller.
Deadlock never happen in this platform.
94% errors of controller has detected by LDU.
87% errors of interface has detected by LDU.
This paper proposed AXI-based post-silicon validation platform.
This platform detect and bypass severe faulty condition
resulting from design error and electrical error.
It can access trace memory in an online manner.
Because we will verify the AXI checker and tracer
later. So this paper can help as to ensure if we can
capture the errors they described.
Some details doesn’t explain in this paper. I will find
these and study them.
Efficient AutomataBased AssertionChecker Synthesis
of SEREs for
Synthesis of PSL
Assertion Checkers –
Enablers of Quality