Transcript Fast A/D sampler Mid semester presentation

Presented By: Tal Goihman, Irit Kaufman
Instructor: Mony Orbach
Spring 2011
Goals

Project Goal:
 Sample with fast A/D to PC memory @
highest possible speed

Semester A Goal:
 Sample to memory onboard virtex6
development board - Done

Semester B Goal:
 Transfer the sampled data from
development board memory to PC memory
through PCI-E
H/W Block Diagram
FMC125
Fast A/D
A/D IC
ML605 development board
FMC
Conn
Virtex6
FPGA
DDR3
PCI-E Connector
PC
ML605 development board
FMC125 Fast A/D
A/D Sampler
The FMC125 is a Quad-Channel ADC that provides
four 8-bit ADC channels enabling simultaneous
sampling of 1, 2, or 4 channels @ 5 , 2.5 , 1.25Gsps
respectively.
 Problems:
 4DSP provides free of charge a reference design only for
4ch @ 1.25Gsps. A reference design for 1ch @ 5Gsps
priced at 2300 EU.
4DSP reference design
Design Block Diagram
UART
MicroBlaze
Bridge
LEDs
intC
FMC125
Aggregator
AXI BUS
AXI
Master
“wormhole”
Switches
Timer
AXI
Slave
Memory
Controller
AXI
Slave
PCI-E
Controller
DDR3
Block Diagram: Main Data Channel

FMC125 delivers data using 4 128-bit lanes of a
proprietary bus running at 125Mhz into the aggregator.

Aggregator unites and synchronizes the different channels
into a 256-bit bus.

AXI Master sends the data over an 256-bit wide AXI bus
running at 200Mhz to the AXI Slave interface of the
Memory Controller.

Memory controller handles Writes to DDR3.

FIFO’s and H/W Flow control in every component’s input
(and some components output) throughout the channel to
achieve highest possible bandwidth.
Memory & Memory controller

512MB DDR3 64-bit @ 400Mhz (800MT/s)

Theoretical bandwidth of
800MT/s * 64bit / 8 = 6.25GB/s

Main channel matched to this theoretical
bandwidth (200Mhz * 256bit /8 = 6.25GB/s)

Memory & controller isn’t perfect, has a
utilization factor.
Block Diagram: MicroBlaze
MicroBlaze is a soft-core processor by
Xilinx.
 Function

 Setup & control all system elements.
 Verification of data in memory using
compare functions and UART output.
AXI Bus background
Xilinx has adopted AXI bus, which is a
standard bus protocol from ARM used in
modern ARM SoC.
 Characteristics

 Memory mapped, 32-bit addresses
 Write Address, write data, write response,
read address, read data
 Variable width, clock & burst length over a
single bus.
AXI write example
Accomplished so far

FMC125 working @ 4ch, 1.25Gsps and
delivering data to the AXI Master through the
aggregator.

AXI Master able to send the data over the AXI
bus

MC receives data from AXI bus and writes it to
DDR3.

We achieved 5.13GB/s Throughput
(82% utilization!)
Test Environment

Verification of sampled data on DDR3 is
accomplished by SW on MicroBlaze
comparing read data with written pattern

FMC125 incoming data is observable
through ChipScope.

Bandwidth was calculated by measuring
the time to write a chunk of data using a
Timer.
Timeline
15/3/12
• Research PCIe problem domain &
possible solutions
15/5/12
• Demonstration of sampled data on PC
memory
30/5/12
7/6/12
• Integration is DONE
• End of semester B presentation
Backup

Documantaion