Transcript Additions to z/Architecture in the IBM System z10

Additions to z/Architecture in the
IBM System z10 Enterprise Class
Dan Greiner
[email protected]
z/Server Architecture
SHARE 112 Session 1291
26 August 2009
IBM® Systems and Technology Group (STG)
© Copyright International Business Machines Corporation 2008-2009.
Topics du Jour
 CPU facilities added in the System z10 EC
► General-Instructions Extension Facility
► Execute-Extension Facility
► Parsing-Enhancement Facility
► Compare-and-Swap-and-Store Facility 2
► Message-Security-Assist Extensions
► Enhanced-DAT Facility
► Configuration-Topology Facility
► Decimal Floating Point (DFP) Facility in Hardware
► Set-Program-Parameters and CPU-Measurement Facilities
 Facility Indications
 Why the new facilities were implemented
 Only CPU facilities discussed, not I/O
SHARE 113, Session 1291
2
General Instructions Extension Facility
 Instruction categories:
► Cache cognizance
► Compare [logical] [immediate] and branch [relative]
► Compare [logical] [immediate] and trap
► Immediate second-operand field
► Relative-long second operand
► Rotate then {AND | OR | XOR | Insert} selected bits
► Miscellany
 Primary motivation: PERFORMANCE!
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Index
General-Instructions Extension Facility:
Cache Cognizance Instructions
Mnemonic
OpCode
EXTRACT CACHE ATTRIBUTE
ECAG
PREFETCH DATA
PREFETCH DATA RELATIVE LONG
Instruction
First Operand
Location
Second Operand
Size Location
Size
EB4C Register
64
S(20)
N/A
PFD
E336
Mask
16
S(20)
MD
PFDRL
C62
Mask
16
RL
MD
Explanation:
N/A
Not applicable
MD
Model Dependent
RL
Relative-long operand; 32-bit immediate value, multiplied by two and added to the current
instruction address, provides the storage location of the operand
S(20)
Storage operand addressed using base, index, and 20-bit signed displacement.
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Index
EXTRACT CACHE ATTRIBUTE (ECAG)
ECAG
R1,R3,D2(B2)
EB R1 R3 B2
R1
DL2
[RSY]
DH2
4C
Result placed in R1.0-63
Selected bits of 2nd-operand address form a code:
Bits 56-59: Attribute Indication:
0 – Extract topology summary (for up to 8 levels)
1 – Extract line size of cache in bytes.
2 – Extract total cache size in bytes.
3 – Extract set-associativity level.
4:15 – Reserved
Bits 60-62: Level indication of cache.
Bit 63: Type indication (0=data, 1=instruction)
Topology Summary in R1 (one byte per cache
level):
Bit 0-3: Reserved, stored as zeros
Bits 4-5: Cache scope, as follows:
00 – Cache level does not exist
01 – Cache is private to the CPU
10 – Cache may be shared
11 – Reserved
Bits 6-7: Cache type, as follows:
00 – Separate instr. & data caches
01 – Only instruction cache
10 – Only data cache
11 – Unified instruction & data cache
Condition Code is Unchanged
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Index
PREFETCH DATA (PFD)
PFD
E3
M1,D2(X2,B2)
M1 X2 B2
DL2
[RXY]
DH2
36
Code:
1 - Prefetch for fetch
2 - Prefetch for store
6 - Release cache line from store, retain for fetch.
7 - Release cache line
Storage Location
All other codes reserved; reserved codes act as no-op
Condition Code is Unchanged
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Index
PREFETCH DATA RELATIVE LONG (PFDRL)
PFDRL
M1,I2
C6 M1 2
[RIL]
I2
x2
Codes same as PFD
Current Instruction Address
+
Storage Location
Condition Code is Unchanged
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Index
General-Instructions Extension Facility:
Compare [Logical] [Immediate] and Branch [Relative]
Mnemonic
OpCode
First Operand
Location
Size Location
Size
COMPARE AND BRANCH
CRB
ECF6
Register
32
Register
32
S(12)
COMPARE AND BRANCH
CGRB
ECE4
Register
64
Register
64
S(12)
COMPARE AND BRANCH RELATIVE
CRJ
EC76
Register
32
Register
32
Relative
COMPARE AND BRANCH RELATIVE
CGRJ
EC64
Register
64
Register
64
Relative
COMPARE IMMEDIATE AND BRANCH
CIB
ECFE Register
32
Immediate
8
S(12)
COMPARE IMMEDIATE AND BRANCH
CGIB
ECFC Register
64
Immediate
8
S(12)
COMPARE IMMEDIATE AND BRANCH RELATIVE
CIJ
EC7E
Register
32
Immediate
8
Relative
COMPARE IMMEDIATE AND BRANCH RELATIVE
CGIJ
EC7C Register
64
Immediate
8
Relative
COMPARE LOGICAL AND BRANCH
CLRB
ECF7
Register
32
Register
32
S(12)
COMPARE LOGICAL AND BRANCH
CLGRB
ECE5
Register
64
Register
64
S(12)
COMPARE LOGICAL AND BRANCH RELATIVE
CLRJ
EC77
Register
32
Register
32
Relative
COMPARE LOGICAL AND BRANCH RELATIVE
CLGRJ
EC65
Register
64
Register
64
Relative
COMPARE LOGICAL IMMEDIATE AND BRANCH
CLIB
ECFF
Register
32
Immediate
8
S(12)
COMPARE LOGICAL IMMEDIATE AND BRANCH
CLGIB
ECFD Register
64
Immediate
8
S(12)
COMPARE LOGICAL IMMEDIATE AND BRANCH
RELATIVE
CLIJ
EC7F
32
Immediate
8
Relative
CLGIJ
EC7D Register
64
Immediate
COMPARE LOGICAL IMMEDIATE AND BRANCH
RELATIVE
S(12)
Storage operand addressed using base, index, and 12-bit unsigned displacement.
8
Relative
Instruction
SHARE 113, Session 1291
Register
Second Operand
Branch
Location
8
Index
COMPARE AND BRANCH (CRB)
(32-bit register signed operands, storage-designated branch)
CRB
R1,R2,M3,D4(B4)
EC R1 R2 B4
R1
//////// //////// //////// ////////
?
//////// //////// //////// ////////
M3 ////
F6
M3 Mask Bit Values:
0 Equal
1 First operand low
2 First operand high
3 --
R1.32-63
M3
TRUE
?
R2
D4
[RRS]
New PSW Instruction Address
R2.32-63
Condition Code is Unchanged
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Index
COMPARE AND BRANCH (CGRB)
(64-bit register signed operands, storage-designated branch)
CGRB
R1,R2,M3,D4(B4)
EC R1 R2 B4
R1
M3 ////
?
E4
M3 Mask Bit Values:
0 Equal
1 First operand low
2 First operand high
3 --
R1.0-63
M3
TRUE
?
R2
D4
[RRS]
New PSW Instruction Address
R2.0-63
Condition Code is Unchanged
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Index
COMPARE AND BRANCH RELATIVE (CRJ)
(32-bit register signed operands, relative-immediate-designated branch)
CRJ
EC R1 R2
R1
//////// //////// //////// ////////
R1,R2,M3,I4
I4
R1.32-63
?
//////// //////// //////// ////////
R2.32-63
M3 ////
76
Mask Bit Values:
0 Equal
1 First operand low
2 First operand high
3 --
M3
TRUE
?
R2
[RIE]
Current Instruction Address
x2
+
New PSW Instruction Address
Condition Code is Unchanged
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Index
COMPARE AND BRANCH RELATIVE (CGRJ)
(64-bit register signed operands, relative-immediate-designated branch)
CGRJ
EC R1 R2
R1
R1,R2,M3,I4
I4
M3
TRUE
?
?
R2.0-63
M3 ////
64
Mask Bit Values:
0 Equal
1 First operand low
2 First operand high
3 --
R1.0-63
R2
[RIE]
Current Instruction Address
x2
+
New PSW Instruction Address
Condition Code is Unchanged
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Index
COMPARE IMMEDIATE AND BRANCH (CIB)
(32-bit register, 8-bit immediate, signed operands;
storage-designated branch)
CIB
R1,I2,M3,D4(B4)
EC R1 M3 B4
R1
//////// //////// //////// ////////
D4
[RIS]
I2
FE
Mask Bit Values:
0 Equal
1 First operand low
2 First operand high
3 --
R1.32-63
M3
TRUE
?
?
SSSSSSSSSSSSS
I2
NEW PSW Instruction Address
Condition Code is Unchanged
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Index
COMPARE IMMEDIATE AND BRANCH (CGIB)
(64-bit register, 8-bit immediate, signed operands;
storage-designated branch)
CGIB
R1,I2,M3,D4(B4)
EC R1 M3 B4
R1
D4
[RIS]
I2
FC
Mask Bit Values:
0 Equal
1 First operand low
2 First operand high
3 --
R1.0-63
M3
TRUE
?
?
SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS
I2
New PSW Instruction Address
Condition Code is Unchanged
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Index
COMPARE IMMEDIATE AND BRANCH RELATIVE (CIJ)
(32-bit register, 8-bit immediate, signed operands;
relative-immediate-designated branch)
CIJ
R1,I2,M3,I4
EC R1 M3
R1
//////// //////// //////// ////////
I4
I2
7E
Mask Bit Values:
0 Equal
1 First operand low
2 First operand high
3 --
R1.32-63
M3
TRUE
?
?
SSSSSSSSSSSSS
[RIE]
Current Instruction Address
I2
x2
+
New PSW Instruction Address
Condition Code is Unchanged
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Index
COMPARE IMMEDIATE AND BRANCH RELATIVE (CGIJ)
(64-bit register, 8-bit immediate, signed operands;
relative-immediate-designated branch)
CGIJ
R1,I2,M3,I4
EC R1 M3
R1
I4
I2
7C
Mask Bit Values:
0 Equal
1 First operand low
2 First operand high
3 --
R1.0-63
M3
TRUE
?
?
SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS
[RIE]
Current Instruction Address
I2
x2
+
New PSW Instruction Address
Condition Code is Unchanged
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Index
COMPARE LOGICAL AND BRANCH (CLRB)
(32-bit register unsigned operands; storage-designated branch)
CLRB
R1,R2,M3,D4(B4)
EC R1 R2 B4
R1
//////// //////// //////// ////////
?
//////// //////// //////// ////////
M3 ////
F7
M3 Mask Bit Values:
0 Equal
1 First operand low
2 First operand high
3 --
R1.32-63
M3
TRUE
?
R2
D4
[RRS]
New PSW Instruction Address
R2.32-63
Condition Code is Unchanged
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Index
COMPARE LOGICAL AND BRANCH (CLGRB)
(64-bit register unsigned operands; storage-designated branch)
CLGRB
R1,R2,M3,D4(B4)
EC R1 R2 B4
R1
M3 ////
?
E5
M3 Mask Bit Values:
0 Equal
1 First operand low
2 First operand high
3 --
R1.0-63
M3
TRUE
?
R2
D4
[RRS]
New PSW Instruction Address
R2.0-63
Condition Code is Unchanged
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Index
COMPARE LOGICAL AND BRANCH RELATIVE (CLRJ)
(32-bit register unsigned operands;
relative-immediate-designated branch)
CLRJ
EC R1 R2
R1
//////// //////// //////// ////////
R1,R2,M3,I4
I4
R1.32-63
?
//////// //////// //////// ////////
R2.32-63
M3 ////
77
Mask Bit Values:
0 Equal
1 First operand low
2 First operand high
3 --
M3
TRUE
?
R2
[RIE]
Current Instruction Address
x2
+
New PSW Instruction Address
Condition Code is Unchanged
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Index
COMPARE LOGICAL AND BRANCH RELATIVE (CLGRJ)
(64-bit register unsigned operands;
relative-immediate-designated branch)
CLGRJ
EC R1 R2
R1
R1,R2,M3,I4
I4
M3
TRUE
?
?
R2.0-63
M3 ////
65
Mask Bit Values:
0 Equal
1 First operand low
2 First operand high
3 --
R1.0-63
R2
[RIE]
Current Instruction Address
x2
+
New PSW Instruction Address
Condition Code is Unchanged
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Index
COMPARE LOGICAL IMMEDIATE AND BRANCH (CLIB)
(32-bit register, 8-bit immediate, unsigned operands;
storage-designated branch)
CLIB
R1,I2,M3,D4(B4)
EC R1 M3 B4
R1
//////// //////// //////// ////////
D4
[RIS]
I2
FF
Mask Bit Values:
0 Equal
1 First operand low
2 First operand high
3 --
R1.32-63
M3
TRUE
?
?
0000000000000000
I2
New PSW Instruction Address
Condition Code is Unchanged
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Index
COMPARE LOGICAL IMMEDIATE AND BRANCH (CLGIB)
(64-bit register, 8-bit immediate, unsigned operands;
storage-designated branch)
CLGIB
R1,I2,M3,D4(B4)
EC R1 M3 B4
R1
D4
[RIS]
I2
FD
Mask Bit Values:
0 Equal
1 First operand low
2 First operand high
3 --
R1.0-63
M3
TRUE
?
?
0000000000000000000000000000000000000
I2
New PSW Instruction Address
Condition Code is Unchanged
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Index
COMPARE LOGICAL IMMEDIATE AND BRANCH RELATIVE (CLIJ)
(32-bit register, 8-bit immediate, unsigned operands;
relative-immediate-designated branch)
CLIJ
R1,I2,M3,I4
EC R1 M3
R1
//////// //////// //////// ////////
I4
I2
7F
Mask Bit Values:
0 Equal
1 First operand low
2 First operand high
3 --
R1.32-63
M3
TRUE
?
?
0000000000000000
[RIE]
Current Instruction Address
I2
x2
+
New PSW Instruction Address
Condition Code is Unchanged
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Index
COMPARE LOGICAL IMMEDIATE AND BRANCH RELATIVE (CLGIJ)
(64-bit register, 8-bit immediate, unsigned operands;
relative-immediate-designated branch)
CLGIJ
R1,I2,M3,I4
EC R1 M3
R1
I4
I2
7D
Mask Bit Values:
0 Equal
1 First operand low
2 First operand high
3 --
R1.0-63
M3
TRUE
?
?
0000000000000000000000000000000000000
[RIE]
Current Instruction Address
I2
x2
+
New PSW Instruction Address
Condition Code is Unchanged
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Index
General-Instructions Extension Facility:
Compare [Logical] [Immediate] and Trap
Mnemonic
OpCode
First Operand
Location
Size Location
Size
COMPARE AND TRAP
CRT
B972
Register
32
Register
32
COMPARE AND TRAP
CGRT
B960
Register
64
Register
64
COMPARE IMMEDIATE AND TRAP
CIT
EC72
Register
32
Immediate
16
COMPARE IMMEDIATE AND TRAP
CGIT
EC70
Register
64
Immediate
16
COMPARE LOGICAL AND TRAP
CLRT
B973
Register
32
Register
32
COMPARE LOGICAL AND TRAP
CLGRT
B961
Register
64
Register
64
COMPARE LOGICAL IMMEDIATE AND TRAP
CLFIT
EC73
Register
32
Immediate
16
COMPARE LOGICAL IMMEDIATE AND TRAP
CLGIT
EC71
Register
64
Immediate
16
Instruction
SHARE 113, Session 1291
Second Operand
25
Index
COMPARE AND TRAP (CRT)
(32-bit register signed operands)
CRT
R1,R2,M3
B972
R1
//////// //////// //////// ////////
[RRF]
M3 //// R1 R2
M3 Mask Bit Values:
0 Equal
1 First operand low
2 First operand high
3 --
R1.32-63
M3
TRUE
?
?
R2
//////// //////// //////// ////////
R2.32-63
Data Exception
Program Interruption
(DXC = FF hex)
Condition Code is Unchanged
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Index
COMPARE AND TRAP (CGRT)
(64-bit register signed operands)
CGRT
B960
R1
R1,R2,M3
[RRF]
M3 //// R1 R2
M3 Mask Bit Values:
0 Equal
1 First operand low
2 First operand high
3 --
R1.0-63
M3
TRUE
?
?
R2
Data Exception
Program Interruption
(DXC = FF hex)
R2.0-63
Condition Code is Unchanged
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Index
COMPARE IMMEDIATE AND TRAP (CIT)
(32-bit register, 16-bit immediate, signed operands)
CIT
R1,I2,M3
EC R1 ////
R1
//////// //////// //////// ////////
I2
[RIE]
M3 ////
72
Mask Bit Values:
0 Equal
1 First operand low
2 First operand high
3 --
R1.32-63
M3
TRUE
?
?
SSSSSSSS
I2
Data Exception
Program Interruption
(DXC = FF hex)
Condition Code is Unchanged
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Index
COMPARE IMMEDIATE AND TRAP (CGIT)
(64-bit register, 16-bit immediate, signed operands)
CGIT
EC R1 ////
R1
R1,I2,M3
I2
[RIE]
M3 ////
70
Mask Bit Values:
0 Equal
1 First operand low
2 First operand high
3 --
R1.0-63
M3
TRUE
?
?
SSSSSSSSSSSSSSSSSSSSSSSSSS
I2
Data Exception
Program Interruption
(DXC = FF hex)
Condition Code is Unchanged
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Index
COMPARE LOGICAL AND TRAP (CLRT)
(32-bit register unsigned operands)
CLRT
B973
R1
//////// //////// //////// ////////
R1,R2,M3
[RRF]
M3 //// R1 R2
M3 Mask Bit Values:
0 Equal
1 First operand low
2 First operand high
3 --
R1.32-63
M3
TRUE
?
?
R2
//////// //////// //////// ////////
R2.32-63
Data Exception
Program Interruption
(DXC = FF hex)
Condition Code is Unchanged
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Index
COMPARE LOGICAL AND TRAP (CLGRT)
(64-bit register unsigned operands)
CLGRT
B961
R1
R1,R2,M3 [RRF]
M3 //// R1 R2
M3 Mask Bit Values:
0 Equal
1 First operand low
2 First operand high
3 --
R1.0-63
M3
TRUE
?
?
R2
Data Exception
Program Interruption
(DXC = FF hex)
R2.0-63
Condition Code is Unchanged
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Index
COMPARE LOGICAL IMMEDIATE AND TRAP (CLFIT)
(32-bit register, 16-bit immediate, unsigned operands)
CLFIT
EC R1 ////
R1
//////// //////// //////// ////////
R1,I2,M3
I2
[RIE]
M3 ////
73
Mask Bit Values:
0 Equal
1 First operand low
2 First operand high
3 --
R1.32-63
M3
TRUE
?
?
0000000000
I2
Data Exception
Program Interruption
(DXC = FF hex)
Condition Code is Unchanged
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Index
COMPARE LOGICAL IMMEDIATE AND TRAP (CLGIT)
(64-bit register, 16-bit immediate, unsigned operands)
CLGIT
EC R1 ////
R1
R1,I2,M3
I2
[RIE]
M3 ////
71
Mask Bit Values:
0 Equal
1 First operand low
2 First operand high
3 --
R1.0-63
M3
TRUE
?
?
00000000000000000000000000000000
I2
Data Exception
Program Interruption
(DXC = FF hex)
Condition Code is Unchanged
SHARE 113, Session 1291
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Index
General-Instructions Extension Facility:
Immediate Second-Operand Instructions
Instruction
Mnemonic
OpCode
ADD IMMEDIATE
ASI
EB6A S(20)
32
S
Immediate 8
S
ADD IMMEDIATE
AGSI
EB7A S(20)
64
S
Immediate 8
S
ADD LOGICAL WITH SIGNED IMMEDIATE
ALSI
EB6E
S(20)
32
U
Immediate 8
S
ADD LOGICAL WITH SIGNED IMMEDIATE
ALGSI
EB7E
S(20)
64
U
Immediate 8
S
COMPARE HALFWORD IMMEDIATE
CHHSI
E554
S(12)
16
S
Immediate 16
S
COMPARE HALFWORD IMMEDIATE
CHSI
E55C
S(12)
32
S
Immediate 16
S
COMPARE HALFWORD IMMEDIATE
CGHSI
E558
S(12)
64
S
Immediate 16
S
COMPARE LOGICAL IMMEDIATE
CLHHSI E555
S(12)
16
U
Immediate 16
U
COMPARE LOGICAL IMMEDIATE
CLFHSI
E55D
S(12)
32
U
Immediate 16
U
COMPARE LOGICAL IMMEDIATE
CLGHSI E556
S(12)
64
U
Immediate 16
U
MOVE [IMMEDIATE]
MVHHI
E544
S(12)
16
S
Immediate 16
S
MOVE [IMMEDIATE]
MVHI
E54C
S(12)
32
S
Immediate 16
S
MOVE [IMMEDIATE]
MVGHI
E548
S(12)
64
S
Immediate 16
S
MULTIPLY SINGLE IMMEDIATE
MSFI
C21
Register 32
S
Immediate 32
S
MULTIPLY SINGLE IMMEDIATE
MSGFI
C20
Register 64
S
Immediate 32
S
SHARE 113, Session 1291
First Operand
Second Operand
Location Size Sign Location
Size Sign
34
Index
ADD IMMEDIATE (ASI)
(32-bit storage and 8-bit immediate, signed operands)
ASI
EB
SSSSSSSSSSSSS
D1(B1),I2
I2
B1
DL1
[SIY]
DH2
6A
I2
+
32-Bit Signed Value
(in storage)
Resulting Condition Code:
0 Result zero; no overflow
1 Result less than zero; no overflow
2 Result greater than zero; no overflow
3 Overflow
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Index
ADD IMMEDIATE (AGSI)
(64-bit storage and 8-bit immediate, signed operands)
AGSI
EB
SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS
D1(B1),I2
I2
B1
DL1
[SIY]
DH2
7A
I2
+
64-Bit Signed Value (in storage)
Resulting Condition Code:
0 Result zero; no overflow
1 Result less than zero; no overflow
2 Result greater than zero; no overflow
3 Overflow
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Index
ADD LOGICAL WITH SIGNED IMMEDIATE (ALSI)
(32-bit unsigned storage and 8-bit signed immediate operands)
ALSI
EB
SSSSSSSSSSSSS
D1(B1),I2
I2
B1
DL1
[SIY]
DH2
6E
I2
+
32-Bit Unsigned Value
(in storage)
Resulting Condition Code:
0 Result zero; no carry
1 Result not zero; no carry
2 Result zero; carry
3 Result not zero; carry
(when I2 is negative)
0 -1 Result not zero; borrow
2 Result zero; no borrow
3 Result not zero; no borrow
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Index
ADD LOGICAL WITH SIGNED IMMEDIATE (ALGSI)
(64-bit unsigned storage and 8-bit signed immediate operands)
ALGSI
EB
SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS
D1(B1),I2
I2
B1
DL1
[SIY]
DH2
7E
I2
+
64-Bit Unsigned Value (in storage)
Resulting Condition Code:
0 Result zero; no carry
1 Result not zero; no carry
2 Result zero; carry
3 Result not zero; carry
(when I2 is negative)
0 -1 Result not zero; borrow
2 Result zero; no borrow
3 Result not zero; no borrow
SHARE 113, Session 1291
38
Index
COMPARE HALFWORD IMMEDIATE (CHHSI)
(16-bit storage, 16-bit immediate, signed operands)
CHHSI
E554
D1(B1),I2
B1
D1
16-bit
Signed
(storage)
[SIL]
I2
?
Resulting Condition Code:
0 Operands equal
1 First operand low
2 First operand high
3 --
SHARE 113, Session 1291
39
Index
COMPARE HALFWORD IMMEDIATE (CHSI)
(32-bit storage, 16-bit immediate, signed operands)
CHSI
E55C
32-bit Signed (storage)
?
D1(B1),I2
B1
D1
SSSSSSSS
[SIL]
I2
I2
Resulting Condition Code:
0 Operands equal
1 First operand low
2 First operand high
3 --
SHARE 113, Session 1291
40
Index
COMPARE HALFWORD IMMEDIATE (CGHSI)
(64-bit storage, 16-bit immediate, signed operands)
CGHSI
E558
D1(B1),I2
B1
D1
[SIL]
I2
64-bit Signed (storage)
?
SSSSSSSSSSSSSSSSSSSSSSSSSSS
I2
Resulting Condition Code:
0 Operands equal
1 First operand low
2 First operand high
3 --
SHARE 113, Session 1291
41
Index
COMPARE LOGICAL IMMEDIATE (CLHHSI)
(16-bit storage, 16-bit immediate, unsigned operands)
CLHHSI
E555
D1(B1),I2
B1
D1
16-bit
Unsigned
(storage)
[SIL]
I2
?
Resulting Condition Code:
0 Operands equal
1 First operand low
2 First operand high
3 --
SHARE 113, Session 1291
42
Index
COMPARE LOGICAL IMMEDIATE (CLFHSI)
(32-bit storage, 16-bit immediate, unsigned operands)
CLFHSI
E55D
32-bit Unsigned (stg.)
?
D1(B1),I2
B1
D1
0000000000
[SIL]
I2
I2
Resulting Condition Code:
0 Operands equal
1 First operand low
2 First operand high
3 --
SHARE 113, Session 1291
43
Index
COMPARE LOGICAL IMMEDIATE (CLGHSI)
(64-bit storage, 16-bit immediate, unsigned operands)
CLGHSI
E559
D1(B1),I2
B1
D1
[SIL]
I2
64-bit Unsigned (storage)
?
00000000000000000000000000000000
I2
Resulting Condition Code:
0 Operands equal
1 First operand low
2 First operand high
3 --
SHARE 113, Session 1291
44
Index
MOVE (MVHHI)
(16-bit storage, 16-bit immediate, signed operands)
MVHHI
E544
D1(B2),I2
B1
D1
[SIL]
I2
16-bit
(storage)
Condition Code is Unchanged
SHARE 113, Session 1291
45
Index
MOVE (MVHI)
(32-bit storage, 16-bit immediate, signed operands)
MVHI
E54C
D1(B2),I2
B1
D1
[SIL]
I2
SSSSSSSS 16-Bit Value
32-bit Signed (storage)
Condition Code is Unchanged
SHARE 113, Session 1291
46
Index
MOVE (MVGHI)
(64-bit storage, 16-bit immediate, signed operands)
MVGHI
E548
D1(B2),I2
B1
D1
[SIL]
I2
SSSSSSSSSSSSSSSSSSSSSSSSSS 16-Bit Value
64-bit Signed (storage)
Condition Code is Unchanged
SHARE 113, Session 1291
47
Index
MULTIPLY SINGLE IMMEDIATE (MSFI)
(32-bit register multiplicand, 32-bit immediate multiplier,
32-bit register product)
MSFI
C2
R1
//////// //////// //////// ////////
X
R1
//////// //////// //////// ////////
R1,I2
R1 1
[RIL]
I2
R1.32-63 (multiplicand)
32-Bit (multiplier)
R1.32-63 (product)
Condition Code is Unchanged
SHARE 113, Session 1291
48
Index
MULTIPLY SINGLE IMMEDIATE (MSGFI)
(64-bit register multiplicand, 32-bit immediate multiplier,
64-bit register product)
MSGFI
C2
R1
R1 0
[RIL]
I2
R1.0-63 (multiplicand)
X
R1
R1,I2
32-Bit (multiplier)
R1.0-63 (product)
Condition Code is Unchanged
SHARE 113, Session 1291
49
Index
General-Instructions Extension Facility:
Relative-Long Second Operands (1 of 2)
Mnemonic
OpCode
First Operand
Location
Size
Location
Size‡
COMPARE RELATIVE LONG
CRL
C6D
Register
32
RL
32
COMPARE RELATIVE LONG
CGFRL
C6C
Register
64
RL
32
COMPARE RELATIVE LONG
CGRL
C68
Register
64
RL
64
COMPARE HALFWORD RELATIVE LONG
CHRL
C65
Register
32
RL
16
COMPARE HALFWORD RELATIVE LONG
CGHRL
C64
Register
64
RL
16
COMPARE LOGICAL RELATIVE LONG
CLRL
C6F
Register
32
RL
32
COMPARE LOGICAL RELATIVE LONG
CLGFRL C6E
Register
64
RL
32
COMPARE LOGICAL RELATIVE LONG
CLGRL
C6A
Register
64
RL
64
COMPARE LOGICAL RELATIVE LONG
CLHRL
C67
Register
32
RL
16
COMPARE LOGICAL RELATIVE LONG
CLGHRL C66
Register
64
RL
16
Instruction
Second Operand
Explanation:
‡
Operand must be aligned on an integral boundary; otherwise, a specification exception is
recognized!
RL
Relative-long operand; 32-bit immediate value, multiplied by two and added to the current
instruction address, provides the storage location of the operand
SHARE 113, Session 1291
50
Index
General-Instructions Extension Facility:
Relative-Long Second Operands (2 of 2)
Mnemonic
OpCode
First Operand
Second Operand
Location Size
Location
Size‡
LOAD RELATIVE LONG
LRL
C4D
Register 32
RL
32
LOAD RELATIVE LONG
LGFRL
C4C
Register 64
RL
32
LOAD RELATIVE LONG
LGRL
C48
Register 64
RL
64
LOAD HALFWORD RELATIVE LONG
LHRL
C45
Register 32
RL
16
LOAD HALFWORD RELATIVE LONG
LGHRL
C44
Register 64
RL
16
LOAD LOGICAL RELATIVE LONG
LLGFRL
C4E
Register 64
RL
32
LOAD LOGICAL HALFWORD RELATIVE LONG
LLHRL
C42
Register 32
RL
16
LOAD LOGICAL HALFWORD RELATIVE LONG
LLGHRL
C46
Register 64
RL
16
STORE RELATIVE LONG
STRL
C4F
Register 32
RL
32
STORE RELATIVE LONG
STGRL
C4B
Register 64
RL
64
STORE HALFWORD RELATIVE LONG
STHRL
C47
Register 16
RL
16
Instruction
Explanation:
‡
Operand must be aligned on an integral boundary; otherwise, a specification exception is
recognized!
RL
Relative-long operand; 32-bit immediate value, multiplied by two and added to the current
instruction address, provides the storage location of the operand
SHARE 113, Session 1291
51
Index
COMPARE RELATIVE LONG (CRL)
(32-bit register and 32-bit relative-immediate, signed operands)
CRL
C6
R1,I2
R1 D
[RIL]
Current Instruction Address
I2
+
x2
R1
//////// //////// //////// ////////
R1.32-63
Signed Word (storage)
?
Resulting Condition Code:
0 Operands equal
1 First operand low
2 First operand high
3 --
SHARE 113, Session 1291
52
Index
COMPARE RELATIVE LONG (CGFRL)
(64-bit register and 32-bit relative-immediate, signed operands)
CGFRL
C6
R1,I2
R1 C
[RIL]
Current Instruction Address
I2
+
x2
SSSSSSSSSSSSSSSSS Signed Word (storage)
R1
R1.0-63
?
Resulting Condition Code:
0 Operands equal
1 First operand low
2 First operand high
3 --
SHARE 113, Session 1291
53
Index
COMPARE RELATIVE LONG (CGRL)
(64-bit register and 64-bit relative-immediate, signed operands)
CGRL
C6
R1,I2
R1 8
[RIL]
Current Instruction Address
I2
+
x2
Signed Doubleword (storage)
R1
R1.0-63
?
Resulting Condition Code:
0 Operands equal
1 First operand low
2 First operand high
3 --
SHARE 113, Session 1291
54
Index
COMPARE HALFWORD RELATIVE LONG (CHRL)
(32-bit register, 16-bit relative-immediate-designated, signed operands)
CHRL
C6
R1,I2
R1 5
[RIL]
I2
Current Instruction Address
x2
+
SSSSSSSS S Halfword
R1
//////// //////// //////// ////////
R1.32-63
?
Resulting Condition Code:
0 Operands equal
1 First operand low
2 First operand high
3 --
SHARE 113, Session 1291
55
Index
COMPARE HALFWORD RELATIVE LONG (CGHRL)
(64-bit register, 16-bit relative-immediate-designated, signed operands)
CGHRL
C6
R1,I2
R1 4
[RIL]
I2
Current Instruction Address
x2
+
SSSSSSSSSSSSSSSSSSSSSSSSSS S Halfword
R1
R1.0-63
?
Resulting Condition Code:
0 Operands equal
1 First operand low
2 First operand high
3 --
SHARE 113, Session 1291
56
Index
COMPARE LOGICAL RELATIVE LONG (CLRL)
(32-bit register and 32-bit relative-immediate, unsigned operands)
CLRL
C6
R1,I2
R1 F
[RIL]
Current Instruction Address
I2
+
x2
Unsigned Word (storage)
R1
//////// //////// //////// ////////
R1.32-63
?
Resulting Condition Code:
0 Operands equal
1 First operand low
2 First operand high
3 --
SHARE 113, Session 1291
57
Index
COMPARE LOGICAL RELATIVE LONG (CLGFRL)
(64-bit register and 32-bit relative-immediate, unsigned operands)
CLGFRL
C6
R1,I2
R1 E
[RIL]
Current Instruction Address
I2
+
x2
000000000000000000000 Unsigned Word (storage)
R1
R1.0-63
?
Resulting Condition Code:
0 Operands equal
1 First operand low
2 First operand high
3 --
SHARE 113, Session 1291
58
Index
COMPARE LOGICAL RELATIVE LONG (CLGRL)
(64-bit register and 64-bit relative-immediate, unsigned operands)
CLGRL
C6
R1,I2
R1 A
[RIL]
Current Instruction Address
I2
+
x2
Unsigned Doubleword (storage)
R1
R1.0-63
?
Resulting Condition Code:
0 Operands equal
1 First operand low
2 First operand high
3 --
SHARE 113, Session 1291
59
Index
COMPARE LOGICAL RELATIVE LONG (CLHRL)
(32-bit register, 16-bit relative-immediate-designated, unsigned operands)
CLHRL
C6
R1,I2
R1 7
[RIL]
I2
Current Instruction Address
x2
+
0000000000 U Halfword
R1
//////// //////// //////// ////////
R1.32-63
?
Resulting Condition Code:
0 Operands equal
1 First operand low
2 First operand high
3 --
SHARE 113, Session 1291
60
Index
COMPARE LOGICAL RELATIVE LONG (CLGHRL)
(64-bit register, 16-bit relative-immediate-designated, unsigned operands)
CLGHRL
C6
R1,I2
R1 6
[RIL]
Current Instruction Address
I2
+
x2
00000000000000000000000000000000 U Halfword
R1
R1.0-63
?
Resulting Condition Code:
0 Operands equal
1 First operand low
2 First operand high
3 --
SHARE 113, Session 1291
61
Index
LOAD RELATIVE LONG (LRL)
(32-bit register and 32-bit relative-immediate operands)
LRL
C4
R1,I2
R1 D
[RIL]
Current Instruction Address
I2
+
x2
Word (storage)
R1
//////// //////// //////// ////////
R1.32-63
Condition Code is Unchanged
SHARE 113, Session 1291
62
Index
LOAD RELATIVE LONG (LGFRL)
(64-bit register and 32-bit relative-immediate, signed operands)
LGFRL
C4
R1,I2
R1 C
[RIL]
Current Instruction Address
I2
+
x2
SSSSSSSSSSSSSSSSS Signed Word (storage)
R1
R1.0-63
Condition Code is Unchanged
SHARE 113, Session 1291
63
Index
LOAD RELATIVE LONG (LGRL)
(64-bit register and 64-bit relative-immediate, signed operands)
LGRL
C4
R1,I2
R1 8
[RIL]
I2
x2
Current Instruction Address
+
Doubleword (storage)
R1
R1.0-63
Condition Code is Unchanged
SHARE 113, Session 1291
64
Index
LOAD HALFWORD RELATIVE LONG (LHRL)
(32-bit register and 16-bit relative-immediate, signed operands)
LHRL
C4
R1,I2
R1 5
[RIL]
Current Instruction Address
I2
+
x2
SSSSSSSS S Halfword
R1
//////// //////// //////// ////////
R1.32-63
Condition Code is Unchanged
SHARE 113, Session 1291
65
Index
LOAD HALFWORD RELATIVE LONG (LGHRL)
(64-bit register and 16-bit relative-immediate, signed operands)
LGHRL
C4
R1,I2
R1 4
[RIL]
Current Instruction Address
I2
+
x2
SSSSSSSSSSSSSSSSSSSSSSSSSS S Halfword
R1
R1.0-63
Condition Code is Unchanged
SHARE 113, Session 1291
66
Index
LOAD LOGICAL RELATIVE LONG (LLGFRL)
(64-bit register and 32-bit relative-immediate, unsigned operands)
LLGFRL
C4
R1,I2
R1 E
[RIL]
Current Instruction Address
I2
+
x2
000000000000000000000 Unsigned Word (storage)
R1
R1.0-63
Condition Code is Unchanged
SHARE 113, Session 1291
67
Index
LOAD LOGICAL HALFWORD RELATIVE LONG (LLHRL)
(32-bit register and 16-bit relative-immediate, unsigned operands)
LLHRL
C4
R1,I2
R1 2
[RIL]
Current Instruction Address
I2
+
x2
0000000000 U Halfword
R1
//////// //////// //////// ////////
R1.32-63
Condition Code is Unchanged
SHARE 113, Session 1291
68
Index
LOAD LOGICAL HALFWORD RELATIVE LONG (LLGHRL)
(64-bit register and 16-bit relative-immediate, unsigned operands)
LLGHRL
C4
R1,I2
R1 6
[RIL]
Current Instruction Address
I2
+
x2
00000000000000000000000000000000 U Halfword
R1
R1.0-63
Condition Code is Unchanged
SHARE 113, Session 1291
69
Index
STORE RELATIVE LONG (STRL)
(32-bit register and 32-bit relative-immediate operands)
STRL
C4
R1,I2
R1 F
[RIL]
Current Instruction Address
I2
+
x2
Word (storage)
R1
//////// //////// //////// ////////
R1.32-63
Condition Code is Unchanged
SHARE 113, Session 1291
70
Index
STORE RELATIVE LONG (STGRL)
(64-bit register and 64-bit relative-immediate, signed operands)
STGRL
C4
R1,I2
R1 B
[RIL]
I2
x2
Current Instruction Address
+
Doubleword (storage)
R1
R1.0-63
Condition Code is Unchanged
SHARE 113, Session 1291
71
Index
STORE HALFWORD RELATIVE LONG (STHRL)
STHRL
C4
R1,I2
R1 7
[RIL]
Current Instruction Address
I2
+
x2
R1
//////// //////// //////// //////// //////// ////////
R1.48-63
Halfword
(storage)
Condition Code is Unchanged
SHARE 113, Session 1291
72
Index
General-Instructions Extension Facility:
Rotate Then xxx Selected Bits
Mnemonic
OpCode
First Operand
Location
Size Location
Size
ROTATE THEN AND SELECTED BITS
RNSBG
EC54
Register
64
Register
V
ROTATE THEN EXCLUSIVE OR SELECTED BITS
RXSBG
EC57
Register
64
Register
V
ROTATE THEN INSERT SELECTED BITS
RISBG
EC55
Register
64
Register
V
ROTATE THEN OR SELECTED BITS
ROSBG EC56
Register
64
Register
V
Instruction
Second Operand
Explanation:
V
Variable number of bits processed, based on I3 and I4 operands of the instruction.
SHARE 113, Session 1291
73
Index
General-Instructions Extension Facility:
ROTATE THEN {AND | OR | XOR} SELECTED BITS
R?SBG
R1,R2,I3,I4[,I5]
EC R1 R2
R2
I3
I4
[RIE]
I5
Mnemonic
RNSBG
ROSBG
RXSBG
5x
Opcode
EC-54
EC-56
EC-57
Function
AND
OR
Exclusive OR
R2.0-63
Rotated Second Operand
I3
R1
SHARE 113, Session 1291
Perform Logical
Operation
on selected
Bits
R1 Bits I3 – I4
I4
Resulting Condition Code:
0 Selected bits zero
1 Selected bits not zero
2 -3 --
74
Index
ROTATE THEN xxx SELECTED BITS (RxSBG)
(continued)
 Bits 2-7 of I5 field are the rotate amount
► Bits rotate to the left; bits that rotate out of bit zero reenter at bit 63
► Negative amount effectively rotates to the right
► I5 field is optional – defaults to zero if not coded
 Bits 2-7 of I3 and I4 fields are starting- and ending-bit positions of
selected bits in R1
► When I3 > I4, wrap-around occurs
► All other bits in R1 are unmodified
 Bit 0 of the I3 field is the Test-Results Control (T)
► When T is one, only CC is set; no change to R1
► HLASM extended mnemonic: RxSBGT
 Only the selected bits are used in determining condition code!
SHARE 113, Session 1291
75
Index
ROTATE THEN INSERT SELECTED BITS (RISBG)
RISBG
R1,R2,I3,I4[,I5]
EC R1 R2
R2
I3
I4
[RIE]
I5
55
R2.0-63
Remaining bits of R1 either:
Rotated Second Operand
I3
R1
SHARE 113, Session 1291
Rotated Bits
are Inserted
into Selected
Bits of R1
R1 Bits I3 – I4
• Left unchanged, or
• Set to zero
I4
Depending on the Z control (bit 0 of
the I4 field)
Resulting Condition Code:
0 Result zero
1 Result less than zero
2 Result greater than zero
3 --
76
Index
ROTATE THEN INSERT SELECTED BITS (RISBG)
(continued)
 Bits 2-7 of I5 field are rotate amount
► Bits rotate to the left; bits that rotate out of bit zero reenter at bit 63
► Negative amount effectively rotates to the right
► I5 field is optional – defaults to zero if not coded
 Bits 2-7 of I3 and I4 fields are starting- and ending-bit position of
selected bits in R1
► When I3 > I4, wrap-around occurs
 Bit 0 of the I4 field is the Zero-Remaining-Bits Control (Z):
► When Z is zero, remaining bits of R1 left unchanged
► When Z is one, remaining bits of R1 set to zero
► HLASM extended mnemonic: RISBGZ
 Condition code set à la LOAD AND TEST (based on all 64 bits)
SHARE 113, Session 1291
77
Index
General-Instructions Extension Facility:
Miscellany
Mnemonic
OpCode
First Operand
Location
Size
Location
Size
COMPARE HALFWORD
CGH
E334
Register
64
S(20)
16
LOAD ADDRESS EXTENDED
LAEY
E375
Register
24/31/64 S(20)
N/A
LOAD AND TEST
LTGF
E332
Register
64
S(20)
32
MULTIPLY
MFY
E35C
Register
64f32
S(20)
32
MULTIPLY HALFWORD
MHY
E37C
Register
32
S(20)
16
Instruction
Second Operand
Explanation:
N/A
Not applicable
S(20)
Storage operand addressed using base, index, and 20-bit signed displacement.
SHARE 113, Session 1291
78
Index
COMPARE HALFWORD (CGH)
(64-bit register, 16-bit storage, signed operands)
CGH
E3
R1,D2(X2,B2)
R1 X2 B2
DL2
[RXY]
DH2
34
SSSSSSSSSSSSSSSSSSSSSSSSSS 16-Bit (stg)
R1
R1.0-63
?
Resulting Condition Code:
0 Operands equal
1 First operand low
2 First operand high
3 --
SHARE 113, Session 1291
79
Index
LOAD ADDRESS EXTENDED (LAEY)
(long-displacement form of LAE)
LAEY
E3
R1,D2(X2,B2)
R1 X2 B2
DL2
[RXY]
DH2
75
PSW
Bits
16-17
GR R1
AR R1
Bits 40-63, 31-63, or 0-63
00
00000000
01
00000000 or AR B2
10
00000001
11
00000002
ALET
Condition Code is Unchanged
SHARE 113, Session 1291
80
Index
LOAD AND TEST (LTGF)
(64-bit register, 32-bit storage, signed operands)
LTGF
E3
R1,D2(X2,B2)
R1 X2 B2
DL2
[RXY]
DH2
32
SSSSSSSSSSSSSSSSS
R1
32-Bit Signed Value
R1.0-63
Resulting Condition Code:
0 Result zero
1 Result less than zero
2 Result greater than zero
3 --
SHARE 113, Session 1291
81
Index
MULTIPLY (MFY)
(32-bit register multiplicand, 32-bit storage multiplier,
64-bit even/odd register product)
MFY
E3
R1
//////// //////// //////// ////////
R1,D2(X2,B2)
R1 X2 B2
DL2
[RXY]
DH2
5C
R1.32-63 (multiplicand)
X
32-Bit (multiplier)
R1
//////// //////// //////// ////////
R1.32-63 (product)
R1+1
//////// //////// //////// ////////
R1+1.32-63 (product)
Condition Code is Unchanged
SHARE 113, Session 1291
82
Index
MULTIPLY HALFWORD (MHY)
(32-bit register multiplicand, 16-bit storage multiplier,
32-bit register product)
MHY
E3
R1
//////// //////// //////// ////////
//////// //////// //////// ////////
R1 X2 B2
DL2
[RXY]
DH2
7C
R1.32-63 (multiplicand)
X
R1
R1,D2(X2,B2)
16-Bit (mult)
R1.32-63 (product)
Condition Code is Unchanged
SHARE 113, Session 1291
83
Index
Execute-Extensions Facility:
 Provides EXECUTE RELATIVE LONG (EXRL)
EXRL
C6
D1(B1),I2
R1 0
[RIL]
Current Instruction Address
I2
+
x2
R1
//////// //////// //////// //////// //////// //////// ////////
56-63
OR
When R1 field is not zero, bits
56-63 of the general register R1
are ORed with bits 8-15 of the
target instruction.
2-, 4-, or 6-Byte Instruction in Storage
Condition Code set by Executed Instruction
SHARE 113, Session 1291
84
Index
Execute-Extensions Facility (2):
 With EXECUTE (EX), interruption-length code is always 4
► Regardless of the length of the executed instruction
 With EXECUTE RELATIVE LONG (EXRL), the interruptionlength code is always 6!
SHARE 113, Session 1291
85
Index
Parsing-Enhancement Facility:
 Two instructions provide enhanced translate-and-test
function
► Left-to-right (TRTE) or right-to-left (TRTRE) processing
► One-byte or two-byte argument characters
– Useful for Unicode or other DBCS support
► One-byte or two-byte function-code table
► Length specified in a register – no EXECUTE required!
► Abbreviated function-code table option for 2-byte argument
characters
– Don’t need 64K or 128K table for certain 2-byte argumentcharacter scanning
SHARE 113, Session 1291
86
Index
Parsing-Enhancement Facility:
TRANSLATE AND TEST EXTENDED (TRTE)
TRANSLATE AND TEST REVERSE EXTENDED (TRTRE)
TRTE R1,R2[,M3]
B9BF
[RRF]
M3 //// R1 R2
M3 Bit Positions:
TRTRE R1,R2[,M3 ] [RRF]
B9BD
R1
R1+1
R2
GR1
M3 //// R1 R2
1 – Function-Code Control (F)
0 = one-byte function codes
1 = two-byte function codes
Pointer to Argument-Characters
Length of Argument-Characters (in bytes)
//////// //////// //////// //////// //////// ////////
2 – Argument-Character Limit (L)
0 = unlimited argument characters
1 = argument character > 255
assumed to be zero
3 – Reserved
Func Code
Pointer to Function-Code Table
SHARE 113, Session 1291
0 – Argument-Character Control (A)
0 = one-byte argument characters
1 = two-byte argument characters
Resulting Condition Code:
0 Entire 1st operand processed w/o
selecting nonzero function code
1 Nonzero function code selected
2 -3 CPU-determined timeout
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Index
Parsing Enhancement Facility:
 TRTE scans left to right
 TRTRE scans right to left
► First-operand argument character used as index into function-code table.
► If function-code table entry is zero, continue with next argument character
(incrementing R1 and decrementing R1+1 by argument-character size)
► If function-code table entry is nonzero, return its value in bits 56-63 or 48-63 of
R2 (depending on setting of F bit)
 Argument-Character Limit (L) bit allows scanning of 2-byte argument
characters with an abbreviated (256 entry) function-code table.
► For most 2-byte character sets, the common delimiting characters (E.g.,
comma, period, parentheses, mathematical symbols, &c.) are in the first 256
positions of the function-code table
► Uninteresting characters (i.e., > 256) are assumed to have a function code of
zero, without actually accessing function-code table.
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Index
Compare-and-Swap-and-Store Facility 2:
CSST
C8
R3
R3+1
D1(B1),D2(B2),R3
R3 2 B1
D1
R3.32-63 (FC=0), R3.0-63 (FC=1)
B2
=
[SSF]
D2
4, 8, or 16 bytes in storage
R3.0-63 and R3+1.0-63 (FC=2)
?
GR0
//////// //////// //////// //////// //////// ////////
SC
FC
Function Code (FC) Values:
0 – Compare R3.32-63 with 4 bytes in
storage
1 – Compare R3.0-63 with 8 bytes in
storage
2 – Compare R3.0-63 and R3+1.0-63
with 16 bytes in storage (new in Z10)
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Index
Compare-and-Swap-and-Store Facility 2
(operands equal):
CSST
C8
R3
D1(B1),D2(B2),R3
R3 2 B1
D1
B2
[SSF]
D2
R3.32-63 (FC=0), R3.0-63 (FC=1)
2SC bytes in storage
R3+1
R3.0-63 and R3+1.0-63 (FC=2)
4, 8, or 16 bytes in storage
GR0
GR1
//////// //////// //////// //////// //////// ////////
SC
FC
=
Block concurrent
interlocked-update
with compare
=
Parameter List Address
Resulting Condition Code:
0 1st & 3rd operands equal;
1st operand replaced by replacement value,
2nd operand replaced by store value
1 1st & 3rd operands unequal; 3rd operand replaced by 1st operand
2 -3 --
SHARE 113, Session 1291
Replacement Value
(4, 8, or 16 bytes)
Store Value (2SC bytes,
1, 2, 4, 8, or 16 bytes)
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Index
Message-Security Assist Extension 2:
 Message-Security-Assist Extension 2:
► Adds advanced-encryption-standard (AES) functions
for message ciphering
– AES-192 algorithm
– AES-256 algorithm
– With or without chaining
 MSA SHA-512 Facility.
► Adds two functions for generating intermediate- and
final-message digests
– SHA-512 algorithm
– Also, SHA-384 (same as SHA-512 algorithm, but with
different initial chaining values).
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Index
Enhanced-DAT Facility:

Current z/Architecture has 4K-byte page frames.
► TLB entry for each translation
► TLB space is very costly, thus limited scope with larger memory.

Enhanced-DAT facility implements substantially-larger frame size
► Similar features in other architectures
► Implemented 1 megabyte frames
► Other future possibilities, 2GB? 4TB??, 8PB???


Assumes operating system does not do a lot of paging (segmenting?)
Changes to control instructions:
► LOAD PAGE TABLE ENTRY ADDRESS – Additional results returned.
► LOAD REAL ADDRESS – Additional results returned.

► SET STORAGE KEY EXTENDED - multiple-block mode (set up to 1M-byte)
Facility enabled by control register 0, bit 40:
► 0 – Classic DAT
► 1 – Enhanced DAT enabled
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Index
Enhanced-DAT Facility:
DAT-Table Entry Changes
Region-Table Entry
Region-Second-Table Origin, Region-Third-Table Origin, or Segment-Table Origin
/ / P / TF I / TT TL
0
52
54
56
58
60
62 63
Segment-Table Entry (FC=0)
Page-Table Origin
F P / / / I C TT / /
C
0
53 54
58 59 60
62 63
Segment-Table Entry (FC=1)
Segment-Frame Absolute Address
/ / / A
ACC
F F P C / / I C TT / /
V
0
44
47 48
C
O
52 53 54 55 56
58 59 60
62 63
Page-Table Entry
Page-Frame Real Address
0 I PC / / / / / / / /
O
0
52
ACC
AV
C
CO
F
FC
Access-control bits for the segment
Validity control for ACC and F bits
Common-segment bit
Change-bit override
Fetch-protection bit for the segment
Format control
SHARE 113, Session 1291
I
P
TF
TL
TT
63
Table-entry invalid bit
DAT-protection bit
Table offset
Table length
Table type
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Index
Enhanced-DAT Facility:
PERFORM FRAME MANAGEMENT FUNCTION
PFMF R1,R2
B9AF
[RRE]
//// //// R1 R2
General Register R1
/ / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / 0 0 0 0 0 0 0 0 0 0 0 0
FMFI
0 0 SC
U FSC 0 M M 0
I
RC
0
Key
ACC
FRC
KF
0
32
44
46 47 48 49
52 53 54 55 56
60 61 62 63
General Register R2
Second-Operand Address (AMODE dependent)
0
33
ACC
C
CF
F
FMFI
FSC
Access-control bits
Change bit of storage key
Clear-frame control
Fetch-protection bit of storage key
Frame-management function indication
Frame-size code (0:4K, 1:1M, 2-7:rsvd.)
SHARE 113, Session 1291
/ / / / / / / / / / / /
40
Key
MC
MR
R
SK
UI
52
63
Storage-protection key
Change-bit update mask
Reference-bit update mask
Reference bit of storage key
Set-key control
Usage indication
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Index
Enhanced-DAT Facility:
PERFORM FRAME MANAGEMENT FUNCTION:
 New control (privileged) instruction:
► Clear up to 1MB of storage
► Set keys for underlying 4K-byte blocks
► Indicate intended usage (for guest running under
z/VM)
 Condition code is unchanged
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Index
Configuration-Topology Facility
 Enhancements to the STORE SYSTEM INFORMATION
instruction:
► Returns new system-information block (SYSIB) 15.1.2
► Indicates topology of processors in the configuration
– Dedicated
– Horizontal polarization
– Vertical polarization
● Low, medium, or high entitlement
 PERFORM TOPOLOGY FUNCTION instruction
► Privileged Operation
► Allows manipulation of topology for the configuration
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Index
Configuration-Topology Facility:
PERFORM TOPOLOGY FUNCTION
PTF R1
[RRE]
B9A2
//// //// R1 ////
/ / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Response Code
0
48
Function Code
56
63
Function Code (FC):
Response Code:
Resulting Condition Code:
0
Request horizontal polarization
0
No reason specified
0
1
Request vertical polarization
1
Already in requested state
Change initiated (FC 0 & 1)
Change-report not pending (FC 2)
2
Check topology-change status
2
Topology change already active
1
Change report pending (FC 2)
2
Request rejected (FC 0 & 1)
3
--
3-255 Reserved
SHARE 113, Session 1291
3-255 Reserved
97
Index
CPU-Measurement Facilities
 Set-program-parameters facility
► SET PROGRAM PARAMETERS (SPP) privileged operation
► Used by the CPU-measurement sampling facility
► Facility bit 40 indicates presence of the facility
 CPU-measurement facility
► CPU-measurement counter facility
► CPU-measurement sampling facility
 Documentation:
► The Set-Program-Parameter and CPU-Measurement Facilities (SA232260-00), http://publibfi.boulder.ibm.com/epubs/pdf/a2322600.pdf
► The CPU-Measurement Facility Extended Counters Definition for z10
(SA23-2261-00), http://publibfi.boulder.ibm.com/epubs/pdf/a2322610.pdf
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Index
CPU-Measurement Counter Facility: Overview
 For each CPU in the configuration:
► Local counter-set-state control register
► Various counters
– Local counters
– Global counters
► Several external-interruption events
– Counter-authorization-change alert
– Loss-of-counter-data alert
– Masked by CR0.58
► Measurement-counter-extraction-authorization control (CR0.15)
► Various instructions
– All privileged operations
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Index
CPU-Measurement Counter Facility: CPU Counter Sets
 Basic counter set
► Cycles, instructions, directory-write and penalty-cycle
counts for L1 instruction and data caches
 Problem-state counter set
► Cycles, instructions, directory-write and penalty-cycle
counts for L1 instruction and data caches
 Crypto-activity counter set
► Functions, cycle, blocked-function, and blocked-cycle
counts for PRNG, SHA, DEA, and AES functions
 Extended counter set (model dependent)
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Index
CPU-Measurement Counter Facility:
Peripheral Counter Sets
 Coprocessor-Group Address
 Coprocessor-Group Counter Set
► Function counts,
► Cycle counts,
► Blocked-function counts, and
► Blocked-cycle counts
for SHA and DEA/AES/MAC functions
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Index
CPU-Measurement Counter Facility: Instructions
 EXTRACT COPROCESSOR GROUP ADDRESS (ECA)
 EXTRACT CPU COUNTER (ECCTR)
 EXTRACT PERIPHERAL COUNTER (EPCTR)
 QUERY COUNTER INFORMATION (QCTRI)
 SET CPU COUNTER (SCCTR)
 SET CPU COUNTER SET CONTROLS (SCCTL)
 SET PERIPHERAL COUNTER (SPCTR)
 SET PERIPHERAL COUNTER SET CONTROLS (SPCTL)
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Index
CPU-Measurement Sampling Facility: Overview
 Two sampling functions
► Basic sampling
► Diagnostic sampling
 Several sampling control registers
► Table-entry-address register
► Data-entry-address register
► Maximum-buffer-size indicator
► Sampling-function-state control register
► Sampling-interval register
► Host indicator
 Several interruption events
 Two instructions:
► QUERY SAMPLING INFORMATION (QSI)
► SET SAMPLING CONTROLS
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Index
CPU-Measurement Sampling Facility: Sampling Buffers
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Index
CPU-Measurement Sampling Facility:
Basic Sampling Data Entry
 PSW-related objects:
►T
DAT-mode bit
►W
Wait-state bit
►P
Problem-state bit
►AS Address-space control
►IA
Instruction address
 Primary ASN (from CR4.48-63)
 Number of unique instructions executed simultaneously
during the sampling cycle
 Host and guest program parameters
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Index
Facility Indication
 New facility indications for System z10 EC stored by STFL* and
STFLE
Bit
Meaning
8
The enhanced-DAT facility is installed
11
The configuration-topology facility is installed
26
The parsing-enhancement facility is installed
33*
The compare-and-swap-and-store facility 2 is installed
34*
The general-instructions-extension facility is installed
35*
The execute-extensions facility is installed.
40*
The set-program-parameters facility is installed.
43*
The DFP facility has high performance.
67*
The CPU-measurement counter facility is installed.
68*
The CPU-measurement sampling facility is installed.
* Note, STFL cannot store beyond bit 31.
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Index
Summary:
 A large variety of facilities added in the System z10 EC
►
►
►
►
►
►
►
►
General-Instructions Extension Facility (72 new)
Execute-Extension Facility (1 new)
Parsing-Enhancement Facility (2 new)
Compare-and-Swap-and-Store Facility 2 (new function)
Message-Security-Assist Extensions (new functions)
Enhanced-DAT Facility (1 new, 3 changed)
Configuration-Topology Facility (1 new, 1 changed)
CPU Measurement Facilities (11 new)
 Potential for:
► Significant performance improvement
► Enhanced capabilities
► Simpler code
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Index
Questions?
Topics
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