Inductor Design for Global Resonant Clock Distribution in a 28-nm CMOS Processor

Visvesh Sathe 3 , Padelis Papadopoulos 2 , Alvin Loke 3 ,

Tarek Khan 1

, Anand Raman 2 , Gerry Vandevalk 3 , Nikolas Provatas 2 , Vincent Ross 1 1 Advanced Micro Devices, Inc.

2 Helic, Inc.

3 Formerly at Advanced Micro Devices, Inc.

2013 DAC Designer/User Track Presentation

Outline

• • • • • • Resonant Clock Distribution Inductor Design and Analysis Challenges Helic VeloceRaptor/X Inductor Extraction using VeloceRaptor/X Silicon Correlation Conclusion

AMD/Helic, Inductor Design for Resonant-clocked Processor Slide 1

Processor Global Clock Distribution

• Significant global clock loading   7-ps clock skew target across > 20-mm 2 core area Constrained clock latency from grid to timing elements AMD “Piledriver” • Typical core-power breakdown consumption gaters 16% bus 5% macros 18% flops 18%

clocking 24%

standard cells 19%

AMD/Helic, Inductor Design for Resonant-clocked Processor Slide 2

Basic Resonant Clocking Operation

|Z clk | ω 0 L tank clk preclk C acgnd

(>>

C clk

)

C clk Z clk frequency

• • • Rely on efficient resonance between L

tank

Efficient operation around ω

0

Driving clock at much lower frequencies and C

clk

near ω

0

 Reduced efficiency, warped clock waveform

AMD/Helic, Inductor Design for Resonant-clocked Processor Slide 3

AMD Resonant Clocking

• 90 inductors distributed over custom power grid, signal wires, and

core circuitry AMD/Helic, Inductor Design for Resonant-clocked Processor Slide 4

Inductor Design

• • • Clock macro, bump pitch constrain inductor size Metal sharing with existing power → cut-aways Centered power straps, HCK tree for  mutual inductance

AMD/Helic, Inductor Design for Resonant-clocked Processor Slide 5

Inductor and Grid Problem Summary

• 87 x 65 μm spiral over 113 x 126 μm custom grid • 12 metal layers (2 thick)   Width: 0.13 to 5.7 μm Thickness: 0.1 to 1.2 μm • >5μm/μm

2 interconnect length to be extracted!

6 5 4 3 2 1 0 M11-M10 M11-M7 Metal levels M11-M3 AMD/Helic, Inductor Design for Resonant-clocked Processor Slide 6

Inductor Design Methodology

• • • • • Goal: Achieve desired L with maximum Q on a highly customized inductor Available design variables   Winding width, outer spacing, inner spacing (NESW) Winding height, winding width Multiple extractions within reasonable time is vital Extraction customization per-metal is crucial   Top metal layers dominate magnetic interaction, lower level metals have minimal interaction Per-metal extraction/merging mode selection (R/C/RC/RLC/RLCk) Process-aware, temperature-sensitive extraction

AMD/Helic, Inductor Design for Resonant-clocked Processor Slide 7

What is VeloceRaptor/X ?

• • • • Rapid, high-capacity multi-GHz EM extraction Maxwell equations-based RLCk model per metal segment Inductance calculations based on magnetic vector potential  Skin and proximity effects, substrate losses, capacitive and magnetic coupling Silicon-proven accuracy    Use model: In situ selection of nets and pin definition Netlist and symbol creation for the marked nets Model annotation and simulation

AMD/Helic, Inductor Design for Resonant-clocked Processor Slide 8

VeloceRaptor/X Offers…

• High capacity and speed • Multithreading support • S-parameters and RLCk netlist output   Temperature-aware model Mixed-mode R/C/RC/RLC/RLCk per any net layer  Layout-dependent effects captured • Direct GDS extraction • Batch-mode support • Numerical network reduction

AMD/Helic, Inductor Design for Resonant-clocked Processor Slide 9

Inductor-over-Grid Model Validation

• • Mixed-mode extraction per net layer:   M11- M x : RLCk M x-1 - M3: RC RLCk extraction below M07 has negligible impact Best tradeoff between model accuracy and runtime/memory requirements No improvement in model accuracy when adding more RLCk layers

Metals

M11-M10: RLCk M11-M9: RLCk M11-M8: RLCk M11-M7: RLCk M11-M6: RLCk M11-M5: RLCk

Density (µm/µm 2 )

3.12E-01 5.78E-01 1.34E+00 2.27E+00 2.93E+00 3.85E+00

Extraction Time (sec) RAM (MB)

517 528 880 1020 3402 6895 10033 14055 3650 6624 12564 21564

Netlist Size (KB)

87 95 96 97 99 102

AMD/Helic, Inductor Design for Resonant-clocked Processor

Increasing interconnect density, runtime, memory requirement

Slide 10

Turnaround Time vs. Metal Density

AMD/Helic, Inductor Design for Resonant-clocked Processor Slide 11

Test Chip Silicon Validation

1,8 5,5 4,5 3,5 2,5 1,5 1,6 1,4 1,2 0,5 1,9 2,5 3,1 3,7 4,3 Frequency (GHz) 4,9 5,5 1,0

•

M11-M06 RLCk Measurement M11-M09 RLCk M11-M07 RLCk M11-M05 RLCk M11-M05 RLCk M11-M10 RLCk M11-M08 RLCk M11-M06 RLCk

Very good agreement between measured and extracted L and Q

AMD/Helic, Inductor Design for Resonant-clocked Processor Slide 12

• • • •

Conclusions

Resonant clocking feature reduces global clock power distribution Use of multiple distributed on-chip inductors poses a significant challenge to inductor extraction – – Metal-rich extraction environment Significant mutual inductance with underlying and adjacent circuits and power grids Exploiting design structure and VeloceRaptor/X capabilities enabled efficient inductor optimization Batch mode and per-metal per-net extraction for extraction of a model with sufficient detail to accurately model silicon behavior.

AMD/Helic, Inductor Design for Resonant-clocked Processor Slide 13